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Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-06-19 01:51:50 +00:00
parent 6b7bb42c36
commit 8557c2bcb8
8 changed files with 147 additions and 52 deletions
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15
lib/Target/ARM/ARMISelLowering.cpp
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@@ -292,6 +292,21 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
if (!Subtarget->isThumb()) {
// Use branch latency information to determine if-conversion limits.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
unsigned Latency = InstrItins.getLatency(TII->get(ARM::BL).getSchedClass());
if (Latency > 1) {
setIfCvtBlockSizeLimit(Latency-1);
if (Latency > 2)
setIfCvtDupBlockSizeLimit(Latency-2);
} else {
setIfCvtBlockSizeLimit(10);
setIfCvtDupBlockSizeLimit(2);
}
}
maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
// Do not enable CodePlacementOpt for now: it currently runs after the
// ARMConstantIslandPass and messes up branch relaxation and placement