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Remove kill flags after if conversion if necessary
When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192482 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
parent
da74817c50
commit
8573384010
@ -23,6 +23,7 @@
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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@ -201,11 +202,12 @@ namespace {
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void PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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LiveRegUnits &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs = 0);
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void CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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LiveRegUnits &Redefs,
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const LiveRegUnits *DontKill = 0,
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bool IgnoreBr = false);
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void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
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@ -964,62 +966,56 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
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BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty());
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}
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/// InitPredRedefs / UpdatePredRedefs - Defs by predicated instructions are
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/// modeled as read + write (sort like two-address instructions). These
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/// routines track register liveness and add implicit uses to if-converted
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/// instructions to conform to the model.
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static void InitPredRedefs(MachineBasicBlock *BB, SmallSet<unsigned,4> &Redefs,
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const TargetRegisterInfo *TRI) {
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for (MachineBasicBlock::livein_iterator I = BB->livein_begin(),
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E = BB->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
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SubRegs.isValid(); ++SubRegs)
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Redefs.insert(*SubRegs);
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}
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}
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static void UpdatePredRedefs(MachineInstr *MI, SmallSet<unsigned,4> &Redefs,
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const TargetRegisterInfo *TRI,
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bool AddImpUse = false) {
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SmallVector<unsigned, 4> Defs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef())
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Defs.push_back(Reg);
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else if (MO.isKill()) {
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for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
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SubRegs.isValid(); ++SubRegs)
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Redefs.erase(*SubRegs);
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}
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}
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MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
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for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
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unsigned Reg = Defs[i];
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if (!Redefs.insert(Reg)) {
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if (AddImpUse)
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// Treat predicated update as read + write.
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MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
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} else {
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for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
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Redefs.insert(*SubRegs);
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}
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}
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}
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static void UpdatePredRedefs(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E,
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SmallSet<unsigned,4> &Redefs,
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/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
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/// values defined in MI which are not live/used by MI.
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static void UpdatePredRedefs(MachineInstr *MI, LiveRegUnits &Redefs,
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const TargetRegisterInfo *TRI) {
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while (I != E) {
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UpdatePredRedefs(I, Redefs, TRI);
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++I;
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for (ConstMIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
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if (!Ops->isReg() || !Ops->isKill())
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continue;
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unsigned Reg = Ops->getReg();
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if (Reg == 0)
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continue;
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Redefs.RemoveReg(Reg, *TRI);
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}
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for (MIBundleOperands Ops(MI); Ops.isValid(); ++Ops) {
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if (!Ops->isReg() || !Ops->isDef())
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continue;
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unsigned Reg = Ops->getReg();
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if (Reg == 0 || Redefs.Contains(Reg, *TRI))
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continue;
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Redefs.AddReg(Reg, *TRI);
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MachineOperand &Op = *Ops;
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MachineInstr *MI = Op.getParent();
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MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
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MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
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}
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}
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/**
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* Remove kill flags from operands with a registers in the @p DontKill set.
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*/
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static void RemoveKills(MachineInstr &MI, const LiveRegUnits &DontKill,
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const MCRegisterInfo &MCRI) {
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for (MIBundleOperands O(&MI); O.isValid(); ++O) {
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if (!O->isReg() || !O->isKill())
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continue;
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if (DontKill.Contains(O->getReg(), MCRI))
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O->setIsKill(false);
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}
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}
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/**
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* Walks a range of machine instructions and removes kill flags for registers
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* in the @p DontKill set.
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*/
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static void RemoveKills(MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator E,
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const LiveRegUnits &DontKill,
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const MCRegisterInfo &MCRI) {
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for ( ; I != E; ++I)
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RemoveKills(*I, DontKill, MCRI);
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}
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/// IfConvertSimple - If convert a simple (split, no rejoin) sub-CFG.
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@ -1052,20 +1048,26 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
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// Initialize liveins to the first BB. These are potentiall redefined by
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// predicated instructions.
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SmallSet<unsigned, 4> Redefs;
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InitPredRedefs(CvtBBI->BB, Redefs, TRI);
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InitPredRedefs(NextBBI->BB, Redefs, TRI);
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LiveRegUnits Redefs;
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Redefs.AddLiveIns(*(CvtBBI->BB), *TRI);
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Redefs.AddLiveIns(*(NextBBI->BB), *TRI);
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// Compute a set of registers which must not be killed by instructions in
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// BB1: This is everything live-in to BB2.
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LiveRegUnits DontKill;
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DontKill.AddLiveIns(*(NextBBI->BB), *TRI);
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if (CvtBBI->BB->pred_size() > 1) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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// Copy instructions in the true block, predicate them, and add them to
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// the entry block.
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs);
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, &DontKill);
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// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
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// explicitly remove CvtBBI as a successor.
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BBI.BB->removeSuccessor(CvtBBI->BB);
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} else {
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RemoveKills(CvtBBI->BB->begin(), CvtBBI->BB->end(), DontKill, *TRI);
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PredicateBlock(*CvtBBI, CvtBBI->BB->end(), Cond, Redefs);
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// Merge converted block into entry block.
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@ -1151,16 +1153,16 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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// Initialize liveins to the first BB. These are potentially redefined by
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// predicated instructions.
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SmallSet<unsigned, 4> Redefs;
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InitPredRedefs(CvtBBI->BB, Redefs, TRI);
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InitPredRedefs(NextBBI->BB, Redefs, TRI);
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LiveRegUnits Redefs;
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Redefs.AddLiveIns(*(CvtBBI->BB), *TRI);
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Redefs.AddLiveIns(*(NextBBI->BB), *TRI);
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bool HasEarlyExit = CvtBBI->FalseBB != NULL;
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if (CvtBBI->BB->pred_size() > 1) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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// Copy instructions in the true block, predicate them, and add them to
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// the entry block.
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, true);
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CopyAndPredicateBlock(BBI, *CvtBBI, Cond, Redefs, 0, true);
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// RemoveExtraEdges won't work if the block has an unanalyzable branch, so
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// explicitly remove CvtBBI as a successor.
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@ -1279,8 +1281,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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// Initialize liveins to the first BB. These are potentially redefined by
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// predicated instructions.
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SmallSet<unsigned, 4> Redefs;
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InitPredRedefs(BBI1->BB, Redefs, TRI);
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LiveRegUnits Redefs;
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Redefs.AddLiveIns(*(BBI1->BB), *TRI);
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// Remove the duplicated instructions at the beginnings of both paths.
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MachineBasicBlock::iterator DI1 = BBI1->BB->begin();
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@ -1307,7 +1309,19 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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--NumDups1;
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}
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UpdatePredRedefs(BBI1->BB->begin(), DI1, Redefs, TRI);
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// Compute a set of registers which must not be killed by instructions in BB1:
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// This is everything used+live in BB2 after the duplicated instructions. We
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// can compute this set by simulating liveness backwards from the end of BB2.
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LiveRegUnits DontKill;
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for (MachineBasicBlock::reverse_instr_iterator I = BBI2->BB->rbegin(),
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E = MachineBasicBlock::reverse_iterator(DI2); I != E; ++I) {
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DontKill.StepBackward(*I, *TRI);
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}
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for (MachineBasicBlock::const_iterator I = BBI1->BB->begin(), E = DI1; I != E;
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++I) {
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Redefs.StepForward(*I, *TRI);
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}
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BBI.BB->splice(BBI.BB->end(), BBI1->BB, BBI1->BB->begin(), DI1);
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BBI2->BB->erase(BBI2->BB->begin(), DI2);
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@ -1325,6 +1339,10 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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}
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BBI1->BB->erase(DI1, BBI1->BB->end());
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// Kill flags in the true block for registers living into the false block
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// must be removed.
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RemoveKills(BBI1->BB->begin(), BBI1->BB->end(), DontKill, *TRI);
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// Remove 'false' block branch and find the last instruction to predicate.
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BBI2->NonPredSize -= TII->RemoveBranch(*BBI2->BB);
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DI2 = BBI2->BB->end();
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@ -1461,7 +1479,7 @@ static bool MaySpeculate(const MachineInstr *MI,
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void IfConverter::PredicateBlock(BBInfo &BBI,
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MachineBasicBlock::iterator E,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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LiveRegUnits &Redefs,
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SmallSet<unsigned, 4> *LaterRedefs) {
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bool AnyUnpred = false;
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bool MaySpec = LaterRedefs != 0;
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@ -1487,7 +1505,7 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
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// If the predicated instruction now redefines a register as the result of
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// if-conversion, add an implicit kill.
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UpdatePredRedefs(I, Redefs, TRI, true);
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UpdatePredRedefs(I, Redefs, TRI);
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}
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std::copy(Cond.begin(), Cond.end(), std::back_inserter(BBI.Predicate));
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@ -1504,7 +1522,8 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
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/// the destination block. Skip end of block branches if IgnoreBr is true.
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void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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LiveRegUnits &Redefs,
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const LiveRegUnits *DontKill,
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bool IgnoreBr) {
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MachineFunction &MF = *ToBBI.BB->getParent();
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@ -1534,7 +1553,11 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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// If the predicated instruction now redefines a register as the result of
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// if-conversion, add an implicit kill.
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UpdatePredRedefs(MI, Redefs, TRI, true);
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UpdatePredRedefs(MI, Redefs, TRI);
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// Some kill flags may not be correct anymore.
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if (DontKill != 0)
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RemoveKills(*MI, *DontKill, *TRI);
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}
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if (!IgnoreBr) {
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30
test/CodeGen/ARM/ifconv-kills.ll
Normal file
30
test/CodeGen/ARM/ifconv-kills.ll
Normal file
@ -0,0 +1,30 @@
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; RUN: llc < %s -march arm -mcpu swift -verify-machineinstrs
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declare i32 @f(i32 %p0, i32 %p1)
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define i32 @foo(i32* %ptr) {
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entry:
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%cmp = icmp ne i32* %ptr, null
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br i1 %cmp, label %if.then, label %if.else
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; present something which can be easily if-converted
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if.then:
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; %R0 should be killed here
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%valt = load i32* %ptr, align 4
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br label %return
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if.else:
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; %R0 should be killed here, however after if-conversion the %R0 kill
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; has to be removed because if.then will follow after this and still
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; read it.
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%addr = getelementptr inbounds i32* %ptr, i32 4
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%vale = load i32* %addr, align 4
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br label %return
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return:
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%phival = phi i32 [ %valt, %if.then ], [ %vale, %if.else ]
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; suggest to bring %phival/%valt/%vale into %R1 (because otherwise there
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; will be no kills in if.then/if.else)
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%retval = call i32 @f (i32 0, i32 %phival)
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ret i32 %retval
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}
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