From 857b1939dabefe931e1fd25b20185153ea389587 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Fri, 1 Apr 2011 22:32:51 +0000 Subject: [PATCH] Fix the instruction table entries for AI1_adde_sube_s_irs multiclass definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 3 +++ test/MC/Disassembler/ARM/arm-tests.txt | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index b0660a00dc6..2f9da43a5b4 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -939,6 +939,7 @@ multiclass AI1_adde_sube_s_irs opcod, string opc, PatFrag opnode, bits<4> Rd; bits<4> Rn; bits<12> imm; + let Inst{31-27} = 0b1110; // non-predicated let Inst{15-12} = Rd; let Inst{19-16} = Rn; let Inst{11-0} = imm; @@ -952,6 +953,7 @@ multiclass AI1_adde_sube_s_irs opcod, string opc, PatFrag opnode, bits<4> Rd; bits<4> Rn; bits<4> Rm; + let Inst{31-27} = 0b1110; // non-predicated let Inst{11-4} = 0b00000000; let isCommutable = Commutable; let Inst{3-0} = Rm; @@ -967,6 +969,7 @@ multiclass AI1_adde_sube_s_irs opcod, string opc, PatFrag opnode, bits<4> Rd; bits<4> Rn; bits<12> shift; + let Inst{31-27} = 0b1110; // non-predicated let Inst{11-0} = shift; let Inst{15-12} = Rd; let Inst{19-16} = Rn; diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 4e39e8e9b3c..c66f8ce9688 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -226,3 +226,10 @@ # CHECK: blx #60 0x0f 0x00 0x00 0xfa + +# CHECK-NOT: adcs r10, r8, r0, asr #6 +# CHECK: adcshi r10, r8, r0, asr #6 +0x40 0xa3 0xb8 0x80 + +# CHECK: adcshi r10, r8, r0, asr r3 +0x50 0xa3 0xb8 0x80