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ARM vector compare to zero instruction assembly parsing support.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-11 23:51:13 +00:00
parent 5093fe69b4
commit 857e1a7b3f
2 changed files with 15 additions and 7 deletions
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15
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -2865,6 +2865,21 @@ bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
Operands.erase(Operands.begin() + 1); Operands.erase(Operands.begin() + 1);
delete Op; delete Op;
} }
// The vector-compare-to-zero instructions have a literal token "#0" at
// the end that comes to here as an immediate operand. Convert it to a
// token to play nicely with the matcher.
if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
static_cast<ARMOperand*>(Operands[5])->isImm()) {
ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
if (CE && CE->getValue() == 0) {
Operands.erase(Operands.begin() + 5);
Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
delete Op;
}
}
return false; return false;
} }

7
test/MC/ARM/neon-cmp-encoding.s
View File

@ -1,11 +1,4 @@
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s
@ XFAIL: *
@ FIXME: We cannot currently test the following instructions, which are
@ currently marked as for-disassembly only in the .td files:
@ - VCEQz
@ - VCGEz, VCLEz
@ - VCGTz, VCLTz
@ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3] @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
vceq.i8 d16, d16, d17 vceq.i8 d16, d16, d17