From 859a18b5833f3566799313ecba8db4916500485b Mon Sep 17 00:00:00 2001
From: Alkis Evlogimenos <alkis@evlogimenos.com>
Date: Sun, 15 Feb 2004 21:37:17 +0000
Subject: [PATCH] Make dense maps keyed on physical registers smallerusing
MRegisterInfo::getNumRegs() instead of MRegisterInfo::FirstVirtualRegister.
Also use MRegisterInfo::is{Physical,Virtual}Register where
appropriate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11477 91177308-0d34-0410-b5e6-96231b3b80d8
---
lib/CodeGen/LiveVariables.cpp | 7 +++----
lib/CodeGen/PrologEpilogInserter.cpp | 2 +-
lib/CodeGen/RegAllocLocal.cpp | 2 +-
lib/CodeGen/RegAllocSimple.cpp | 2 +-
lib/Target/X86/PeepholeOptimizer.cpp | 2 +-
lib/Target/X86/Printer.cpp | 2 +-
lib/Target/X86/X86AsmPrinter.cpp | 2 +-
lib/Target/X86/X86CodeEmitter.cpp | 2 +-
lib/Target/X86/X86PeepholeOpt.cpp | 2 +-
9 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 420cb4443ec..0554bae87be 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -187,10 +187,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
// physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks.
//
- MachineInstr *PhysRegInfoA[MRegisterInfo::FirstVirtualRegister];
- bool PhysRegUsedA[MRegisterInfo::FirstVirtualRegister];
- std::fill(PhysRegInfoA, PhysRegInfoA+MRegisterInfo::FirstVirtualRegister,
- (MachineInstr*)0);
+ MachineInstr *PhysRegInfoA[RegInfo->getNumRegs()];
+ bool PhysRegUsedA[RegInfo->getNumRegs()];
+ std::fill(PhysRegInfoA, PhysRegInfoA+RegInfo->getNumRegs(), (MachineInstr*)0);
PhysRegInfo = PhysRegInfoA;
PhysRegUsed = PhysRegUsedA;
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 30e7eb69588..4082019dfc6 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -98,7 +98,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
return;
// This bitset contains an entry for each physical register for the target...
- std::vector<bool> ModifiedRegs(MRegisterInfo::FirstVirtualRegister);
+ std::vector<bool> ModifiedRegs(RegInfo->getNumRegs());
unsigned MaxCallFrameSize = 0;
bool HasCalls = false;
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index f9abd68e14a..1ca7f0c440c 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -53,7 +53,7 @@ namespace {
std::vector<unsigned> Virt2PhysRegMap;
unsigned &getVirt2PhysRegMapSlot(unsigned VirtReg) {
- assert(VirtReg >= MRegisterInfo::FirstVirtualRegister &&"Illegal VREG #");
+ assert(MRegisterInfo::isVirtualRegister(VirtReg) &&"Illegal VREG #");
assert(VirtReg-MRegisterInfo::FirstVirtualRegister <Virt2PhysRegMap.size()
&& "VirtReg not in map!");
return Virt2PhysRegMap[VirtReg-MRegisterInfo::FirstVirtualRegister];
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index e313004ff48..a81edda858c 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -154,7 +154,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Made to combat the incorrect allocation of r2 = add r1, r1
std::map<unsigned, unsigned> Virt2PhysRegMap;
- RegsUsed.resize(MRegisterInfo::FirstVirtualRegister);
+ RegsUsed.resize(RegInfo->getNumRegs());
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp
index 0c159e16985..42c985d2d63 100644
--- a/lib/Target/X86/PeepholeOptimizer.cpp
+++ b/lib/Target/X86/PeepholeOptimizer.cpp
@@ -164,7 +164,7 @@ namespace {
// getDefinition - Return the machine instruction that defines the specified
// SSA virtual register.
MachineInstr *getDefinition(unsigned Reg) {
- assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
+ assert(MRegisterInfo::isVirtualRegister(Reg) &&
"use-def chains only exist for SSA registers!");
assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
"Unknown register number!");
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index f591612aea3..31ac00f7293 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -399,7 +399,7 @@ void Printer::printOp(const MachineOperand &MO,
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
- if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
// Bug Workaround: See note in Printer::doInitialization about %.
O << "%" << RI.get(MO.getReg()).Name;
else
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index f591612aea3..31ac00f7293 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -399,7 +399,7 @@ void Printer::printOp(const MachineOperand &MO,
}
// FALLTHROUGH
case MachineOperand::MO_MachineRegister:
- if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
+ if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
// Bug Workaround: See note in Printer::doInitialization about %.
O << "%" << RI.get(MO.getReg()).Name;
else
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 4a66230c5f6..a28d0ee86db 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -329,7 +329,7 @@ static unsigned getX86RegNum(unsigned RegNo) {
case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
return RegNo-X86::ST0;
default:
- assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
+ assert(MRegisterInfo::isVirtualRegister(RegNo) &&
"Unknown physical register!");
assert(0 && "Register allocator hasn't allocated reg correctly yet!");
return 0;
diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp
index 0c159e16985..42c985d2d63 100644
--- a/lib/Target/X86/X86PeepholeOpt.cpp
+++ b/lib/Target/X86/X86PeepholeOpt.cpp
@@ -164,7 +164,7 @@ namespace {
// getDefinition - Return the machine instruction that defines the specified
// SSA virtual register.
MachineInstr *getDefinition(unsigned Reg) {
- assert(Reg >= MRegisterInfo::FirstVirtualRegister &&
+ assert(MRegisterInfo::isVirtualRegister(Reg) &&
"use-def chains only exist for SSA registers!");
assert(Reg - MRegisterInfo::FirstVirtualRegister < DefiningInst.size() &&
"Unknown register number!");