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R600: Implement getRsqrtEstimate
Only do for f32 since I'm unclear on both what this is expecting for the refinement steps in terms of accuracy, and what f64 instruction actually provides. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225827 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2567,6 +2567,24 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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}
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}
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SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
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DAGCombinerInfo &DCI,
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unsigned &RefinementSteps,
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bool &UseOneConstNR) const {
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SelectionDAG &DAG = DCI.DAG;
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EVT VT = Operand.getValueType();
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if (VT == MVT::f32) {
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RefinementSteps = 0;
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return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
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}
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// TODO: There is also f64 rsq instruction, but the documentation is less
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// clear on its precision.
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return SDValue();
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}
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static void computeKnownBitsForMinMax(const SDValue Op0,
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const SDValue Op1,
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APInt &KnownZero,
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@ -167,6 +167,11 @@ public:
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const char* getTargetNodeName(unsigned Opcode) const override;
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SDValue getRsqrtEstimate(SDValue Operand,
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DAGCombinerInfo &DCI,
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unsigned &RefinementSteps,
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bool &UseOneConstNR) const override;
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virtual SDNode *PostISelFolding(MachineSDNode *N,
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SelectionDAG &DAG) const {
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return N;
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@ -1,4 +1,7 @@
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; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s
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; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x)
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; CHECK: {{^}}fsqrt_f32:
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; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}}
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@ -1,6 +1,7 @@
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare float @llvm.sqrt.f32(float) nounwind readnone
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declare double @llvm.sqrt.f64(double) nounwind readnone
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@ -36,3 +37,38 @@ define void @rsq_f32_sgpr(float addrspace(1)* noalias %out, float %val) nounwind
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store float %div, float addrspace(1)* %out, align 4
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ret void
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}
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; Recognize that this is rsqrt(a) * rcp(b) * c,
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; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
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; SI-LABEL: @rsqrt_fmul
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; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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; SI-UNSAFE-DAG: v_rsq_f32_e32 [[RSQA:v[0-9]+]], [[A]]
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; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCPB:v[0-9]+]], [[B]]
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; SI-UNSAFE-DAG: v_mul_f32_e32 [[TMP:v[0-9]+]], [[RCPB]], [[RSQA]]
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; SI-UNSAFE: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
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; SI-UNSAFE: buffer_store_dword [[RESULT]]
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; SI-SAFE-NOT: v_rsq_f32
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; SI: s_endpgm
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define void @rsqrt_fmul(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%out.gep = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.0 = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.2 = getelementptr float addrspace(1)* %gep.0, i32 2
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%a = load float addrspace(1)* %gep.0
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%b = load float addrspace(1)* %gep.1
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%c = load float addrspace(1)* %gep.2
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%x = call float @llvm.sqrt.f32(float %a)
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%y = fmul float %x, %b
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%z = fdiv float %c, %y
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store float %z, float addrspace(1)* %out.gep
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ret void
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}
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