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Implement optimizeCompareInstr for PPC
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
parent
a88a016f2d
commit
860c08cad5
@ -32,6 +32,7 @@
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/raw_ostream.h"
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#define GET_INSTRMAP_INFO
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#define GET_INSTRINFO_CTOR
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#define GET_INSTRINFO_CTOR
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#include "PPCGenInstrInfo.inc"
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#include "PPCGenInstrInfo.inc"
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@ -1055,6 +1056,305 @@ bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
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}
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}
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}
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}
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bool PPCInstrInfo::analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const {
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: return false;
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case PPC::CMPWI:
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case PPC::CMPLWI:
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case PPC::CMPDI:
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case PPC::CMPLDI:
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SrcReg = MI->getOperand(1).getReg();
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SrcReg2 = 0;
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Value = MI->getOperand(2).getImm();
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Mask = 0xFFFF;
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return true;
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case PPC::CMPW:
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case PPC::CMPLW:
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case PPC::CMPD:
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case PPC::CMPLD:
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case PPC::FCMPUS:
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case PPC::FCMPUD:
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SrcReg = MI->getOperand(1).getReg();
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SrcReg2 = MI->getOperand(2).getReg();
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return true;
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}
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}
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bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
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unsigned SrcReg, unsigned SrcReg2,
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int Mask, int Value,
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const MachineRegisterInfo *MRI) const {
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int OpC = CmpInstr->getOpcode();
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unsigned CRReg = CmpInstr->getOperand(0).getReg();
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bool isFP = OpC == PPC::FCMPUS || OpC == PPC::FCMPUD;
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unsigned CRRecReg = isFP ? PPC::CR1 : PPC::CR0;
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// The record forms set the condition register based on a signed comparison
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// with zero (so says the ISA manual). This is not as straightforward as it
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// seems, however, because this is always a 64-bit comparison on PPC64, even
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// for instructions that are 32-bit in nature (like slw for example).
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// So, on PPC32, for unsigned comparisons, we can use the record forms only
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// for equality checks (as those don't depend on the sign). On PPC64,
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// we are restricted to equality for unsigned 64-bit comparisons and for
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// signed 32-bit comparisons the applicability is more restricted.
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bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
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bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW;
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bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW;
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bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD;
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// Get the unique definition of SrcReg.
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MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
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if (!MI) return false;
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int MIOpC = MI->getOpcode();
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bool equalityOnly = false;
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bool noSub = false;
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if (isPPC64) {
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if (is32BitSignedCompare) {
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// We can perform this optimization only if MI is sign-extending.
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if (MIOpC == PPC::SRAW || MIOpC == PPC::SRAWo ||
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MIOpC == PPC::SRAWI || MIOpC == PPC::SRAWIo ||
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MIOpC == PPC::EXTSB || MIOpC == PPC::EXTSBo ||
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MIOpC == PPC::EXTSH || MIOpC == PPC::EXTSHo ||
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MIOpC == PPC::EXTSW || MIOpC == PPC::EXTSWo) {
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noSub = true;
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} else
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return false;
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} else if (is32BitUnsignedCompare) {
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// We can perform this optimization, equality only, if MI is
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// zero-extending.
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if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
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MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||
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MIOpC == PPC::SRW || MIOpC == PPC::SRWo) {
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noSub = true;
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equalityOnly = true;
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} else
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return false;
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} else if (!isFP)
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equalityOnly = is64BitUnsignedCompare;
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} else if (!isFP)
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equalityOnly = is32BitUnsignedCompare;
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if (equalityOnly) {
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// We need to check the uses of the condition register in order to reject
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// non-equality comparisons.
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for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
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IE = MRI->use_end(); I != IE; ++I) {
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MachineInstr *UseMI = &*I;
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if (UseMI->getOpcode() == PPC::BCC) {
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unsigned Pred = UseMI->getOperand(0).getImm();
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if (Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE)
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continue;
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return false;
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} else if (UseMI->getOpcode() == PPC::ISEL ||
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UseMI->getOpcode() == PPC::ISEL8) {
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unsigned SubIdx = UseMI->getOperand(3).getSubReg();
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if (SubIdx == PPC::sub_eq)
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continue;
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return false;
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} else
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return false;
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}
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}
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// Get ready to iterate backward from CmpInstr.
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MachineBasicBlock::iterator I = CmpInstr, E = MI,
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B = CmpInstr->getParent()->begin();
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// Scan forward to find the first use of the compare.
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for (MachineBasicBlock::iterator EL = CmpInstr->getParent()->end();
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I != EL; ++I) {
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bool FoundUse = false;
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for (MachineRegisterInfo::use_iterator J = MRI->use_begin(CRReg),
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JE = MRI->use_end(); J != JE; ++J)
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if (&*J == &*I) {
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FoundUse = true;
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break;
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}
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if (FoundUse)
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break;
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}
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// Early exit if we're at the beginning of the BB.
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if (I == B) return false;
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// There are two possible candidates which can be changed to set CR[01].
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// One is MI, the other is a SUB instruction.
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// For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
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MachineInstr *Sub = NULL;
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if (SrcReg2 != 0)
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// MI is not a candidate for CMPrr.
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MI = NULL;
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// FIXME: Conservatively refuse to convert an instruction which isn't in the
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// same BB as the comparison. This is to allow the check below to avoid calls
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// (and other explicit clobbers); instead we should really check for these
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// more explicitly (in at least a few predecessors).
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else if (MI->getParent() != CmpInstr->getParent() || Value != 0) {
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// PPC does not have a record-form SUBri.
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return false;
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}
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// Search for Sub.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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--I;
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for (; I != E && !noSub; --I) {
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const MachineInstr &Instr = *I;
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unsigned IOpC = Instr.getOpcode();
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if (&*I != CmpInstr && (
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Instr.modifiesRegister(CRRecReg, TRI) ||
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Instr.readsRegister(CRRecReg, TRI)))
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// This instruction modifies or uses the record condition register after
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// the one we want to change. While we could do this transformation, it
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// would likely not be profitable. This transformation removes one
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// instruction, and so even forcing RA to generate one move probably
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// makes it unprofitable.
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return false;
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// Check whether CmpInstr can be made redundant by the current instruction.
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if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
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OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
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(IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
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((Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getReg() == SrcReg2) ||
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(Instr.getOperand(1).getReg() == SrcReg2 &&
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Instr.getOperand(2).getReg() == SrcReg))) {
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Sub = &*I;
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break;
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}
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if (isFP && (IOpC == PPC::FSUB || IOpC == PPC::FSUBS) &&
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((Instr.getOperand(1).getReg() == SrcReg &&
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Instr.getOperand(2).getReg() == SrcReg2) ||
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(Instr.getOperand(1).getReg() == SrcReg2 &&
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Instr.getOperand(2).getReg() == SrcReg))) {
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Sub = &*I;
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break;
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}
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if (I == B)
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// The 'and' is below the comparison instruction.
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return false;
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}
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// Return false if no candidates exist.
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if (!MI && !Sub)
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return false;
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// The single candidate is called MI.
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if (!MI) MI = Sub;
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int NewOpC = -1;
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MIOpC = MI->getOpcode();
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if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
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NewOpC = MIOpC;
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else {
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NewOpC = PPC::getRecordFormOpcode(MIOpC);
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if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1)
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NewOpC = MIOpC;
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}
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// FIXME: On the non-embedded POWER architectures, only some of the record
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// forms are fast, and we should use only the fast ones.
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// The defining instruction has a record form (or is already a record
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// form). It is possible, however, that we'll need to reverse the condition
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// code of the users.
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if (NewOpC == -1)
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return false;
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SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4>
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OperandsToUpdate;
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SmallVector<std::pair<MachineOperand*, MachineOperand*>, 4>
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OperandsToSwap;
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// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
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// needs to be updated to be based on SUB. Push the condition code
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// operands to OperandsToUpdate. If it is safe to remove CmpInstr, the
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// condition code of these operands will be modified.
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bool ShouldSwap = false;
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if (Sub) {
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ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
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Sub->getOperand(2).getReg() == SrcReg;
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// The operands to subf are the opposite of sub, so only in the fixed-point
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// case, invert the order.
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if (!isFP)
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ShouldSwap = !ShouldSwap;
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}
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if (ShouldSwap)
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for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
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IE = MRI->use_end(); I != IE; ++I) {
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MachineInstr *UseMI = &*I;
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if (UseMI->getOpcode() == PPC::BCC) {
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PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
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if (ShouldSwap)
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OperandsToUpdate.push_back(std::make_pair(&((*I).getOperand(0)),
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PPC::InvertPredicate(Pred)));
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} else if (UseMI->getOpcode() == PPC::ISEL ||
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UseMI->getOpcode() == PPC::ISEL8) {
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if (ShouldSwap)
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OperandsToSwap.push_back(std::make_pair(&((*I).getOperand(1)),
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&((*I).getOperand(2))));
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} else // We need to abort on a user we don't understand.
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return false;
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}
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// Create a new virtual register to hold the value of the CR set by the
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// record-form instruction. If the instruction was not previously in
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// record form, then set the kill flag on the CR.
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CmpInstr->eraseFromParent();
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MachineBasicBlock::iterator MII = MI;
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BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
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get(TargetOpcode::COPY), CRReg)
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.addReg(CRRecReg, MIOpC != NewOpC ? RegState::Kill : 0);
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if (MIOpC != NewOpC) {
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// We need to be careful here: we're replacing one instruction with
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// another, and we need to make sure that we get all of the right
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// implicit uses and defs. On the other hand, the caller may be holding
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// an iterator to this instruction, and so we can't delete it (this is
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// specifically the case if this is the instruction directly after the
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// compare).
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const MCInstrDesc &NewDesc = get(NewOpC);
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MI->setDesc(NewDesc);
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if (NewDesc.ImplicitDefs)
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for (const uint16_t *ImpDefs = NewDesc.getImplicitDefs();
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*ImpDefs; ++ImpDefs)
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if (!MI->definesRegister(*ImpDefs))
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MI->addOperand(*MI->getParent()->getParent(),
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MachineOperand::CreateReg(*ImpDefs, true, true));
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if (NewDesc.ImplicitUses)
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for (const uint16_t *ImpUses = NewDesc.getImplicitUses();
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*ImpUses; ++ImpUses)
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if (!MI->readsRegister(*ImpUses))
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MI->addOperand(*MI->getParent()->getParent(),
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MachineOperand::CreateReg(*ImpUses, false, true));
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}
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// Modify the condition code of operands in OperandsToUpdate.
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// Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
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// be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
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for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
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OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
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for (unsigned i = 0, e = OperandsToSwap.size(); i < e; i++)
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std::swap(*OperandsToSwap[i].first, *OperandsToSwap[i].second);
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return true;
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}
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/// GetInstSize - Return the number of bytes of code the specified
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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/// instruction may be. This returns the maximum number of bytes.
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///
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///
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@ -205,6 +205,18 @@ public:
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virtual bool isPredicable(MachineInstr *MI) const;
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virtual bool isPredicable(MachineInstr *MI) const;
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// Comparison optimization.
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virtual bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const;
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr,
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unsigned SrcReg, unsigned SrcReg2,
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int Mask, int Value,
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const MachineRegisterInfo *MRI) const;
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/// GetInstSize - Return the number of bytes of code the specified
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/// GetInstSize - Return the number of bytes of code the specified
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/// instruction may be. This returns the maximum number of bytes.
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/// instruction may be. This returns the maximum number of bytes.
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///
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///
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101
test/CodeGen/PowerPC/optcmp.ll
Normal file
101
test/CodeGen/PowerPC/optcmp.ll
Normal file
@ -0,0 +1,101 @@
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
|
||||||
|
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
|
||||||
|
target triple = "powerpc64-unknown-linux-gnu"
|
||||||
|
|
||||||
|
define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%sub = sub nsw i32 %a, %b
|
||||||
|
store i32 %sub, i32* %c, align 4, !tbaa !0
|
||||||
|
%cmp = icmp sgt i32 %a, %b
|
||||||
|
%cond = select i1 %cmp, i32 %a, i32 %b
|
||||||
|
ret i32 %cond
|
||||||
|
|
||||||
|
; CHECK: @foo
|
||||||
|
; CHECK-NOT: subf.
|
||||||
|
}
|
||||||
|
|
||||||
|
define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%shl = shl i32 %a, %b
|
||||||
|
store i32 %shl, i32* %c, align 4, !tbaa !0
|
||||||
|
%cmp = icmp sgt i32 %shl, 0
|
||||||
|
%conv = zext i1 %cmp to i32
|
||||||
|
ret i32 %conv
|
||||||
|
|
||||||
|
; CHECK: @foo2
|
||||||
|
; CHECK-NOT: slw.
|
||||||
|
}
|
||||||
|
|
||||||
|
define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%sub = sub nsw i64 %a, %b
|
||||||
|
store i64 %sub, i64* %c, align 8, !tbaa !3
|
||||||
|
%cmp = icmp sgt i64 %a, %b
|
||||||
|
%cond = select i1 %cmp, i64 %a, i64 %b
|
||||||
|
ret i64 %cond
|
||||||
|
|
||||||
|
; CHECK: @fool
|
||||||
|
; CHECK: subf. [[REG:[0-9]+]], 4, 3
|
||||||
|
; CHECK: isel 3, 3, 4, 1
|
||||||
|
; CHECK: std [[REG]], 0(5)
|
||||||
|
}
|
||||||
|
|
||||||
|
define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%sub = sub nsw i64 %a, %b
|
||||||
|
store i64 %sub, i64* %c, align 8, !tbaa !3
|
||||||
|
%cmp = icmp sle i64 %a, %b
|
||||||
|
%cond = select i1 %cmp, i64 %a, i64 %b
|
||||||
|
ret i64 %cond
|
||||||
|
|
||||||
|
; CHECK: @foolb
|
||||||
|
; CHECK: subf. [[REG:[0-9]+]], 4, 3
|
||||||
|
; CHECK: isel 3, 4, 3, 1
|
||||||
|
; CHECK: std [[REG]], 0(5)
|
||||||
|
}
|
||||||
|
|
||||||
|
define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%shl = shl i64 %a, %b
|
||||||
|
store i64 %shl, i64* %c, align 8, !tbaa !3
|
||||||
|
%cmp = icmp sgt i64 %shl, 0
|
||||||
|
%conv1 = zext i1 %cmp to i64
|
||||||
|
ret i64 %conv1
|
||||||
|
|
||||||
|
; CHECK: @foo2l
|
||||||
|
; CHECK: sld. 4, 3, 4
|
||||||
|
; CHECK: std 4, 0(5)
|
||||||
|
}
|
||||||
|
|
||||||
|
define double @food(double %a, double %b, double* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%sub = fsub double %a, %b
|
||||||
|
store double %sub, double* %c, align 8, !tbaa !3
|
||||||
|
%cmp = fcmp ogt double %a, %b
|
||||||
|
%cond = select i1 %cmp, double %a, double %b
|
||||||
|
ret double %cond
|
||||||
|
|
||||||
|
; CHECK: @food
|
||||||
|
; CHECK: fsub. 0, 1, 2
|
||||||
|
; CHECK: stfd 0, 0(5)
|
||||||
|
}
|
||||||
|
|
||||||
|
define float @foof(float %a, float %b, float* nocapture %c) #0 {
|
||||||
|
entry:
|
||||||
|
%sub = fsub float %a, %b
|
||||||
|
store float %sub, float* %c, align 4, !tbaa !3
|
||||||
|
%cmp = fcmp ogt float %a, %b
|
||||||
|
%cond = select i1 %cmp, float %a, float %b
|
||||||
|
ret float %cond
|
||||||
|
|
||||||
|
; CHECK: @foof
|
||||||
|
; CHECK: fsubs. 0, 1, 2
|
||||||
|
; CHECK: stfs 0, 0(5)
|
||||||
|
}
|
||||||
|
|
||||||
|
!0 = metadata !{metadata !"int", metadata !1}
|
||||||
|
!1 = metadata !{metadata !"omnipotent char", metadata !2}
|
||||||
|
!2 = metadata !{metadata !"Simple C/C++ TBAA"}
|
||||||
|
!3 = metadata !{metadata !"long", metadata !1}
|
||||||
|
!4 = metadata !{metadata !"any pointer", metadata !1}
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user