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Change TargetLowering::getRepRegClassFor to take an MVT, instead of

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EVT.

Accordingly, change RegDefIter to contain MVTs instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170140 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Patrik Hagglund 2012-12-13 18:45:35 +00:00
parent d14baf450b
commit 860e7cdab9
5 changed files with 14 additions and 15 deletions
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5
include/llvm/Target/TargetLowering.h
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@ -243,9 +243,8 @@ public:
/// legal super-reg register class for the register class of the value type. /// legal super-reg register class for the register class of the value type.
/// For example, on i386 the rep register class for i8, i16, and i32 are GR32; /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
/// while the rep register class is GR64 on x86_64. /// while the rep register class is GR64 on x86_64.
virtual const TargetRegisterClass *getRepRegClassFor(EVT VT) const { virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
assert(VT.isSimple() && "getRepRegClassFor called on illegal type!"); const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
const TargetRegisterClass *RC = RepRegClassForVT[VT.getSimpleVT().SimpleTy];
return RC; return RC;
} }

2
lib/CodeGen/MachineLICM.cpp
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@ -780,7 +780,7 @@ MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
unsigned Reg, unsigned OpIdx, unsigned Reg, unsigned OpIdx,
unsigned &RCId, unsigned &RCCost) const { unsigned &RCId, unsigned &RCCost) const {
const TargetRegisterClass *RC = MRI->getRegClass(Reg); const TargetRegisterClass *RC = MRI->getRegClass(Reg);
EVT VT = *RC->vt_begin(); MVT VT = *RC->vt_begin();
if (VT == MVT::Untyped) { if (VT == MVT::Untyped) {
RCId = RC->getID(); RCId = RC->getID();
RCCost = 1; RCCost = 1;

16
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -268,7 +268,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
const TargetRegisterInfo *TRI, const TargetRegisterInfo *TRI,
unsigned &RegClass, unsigned &Cost, unsigned &RegClass, unsigned &Cost,
const MachineFunction &MF) { const MachineFunction &MF) {
EVT VT = RegDefPos.GetValue(); MVT VT = RegDefPos.GetValue();
// Special handling for untyped values. These values can only come from // Special handling for untyped values. These values can only come from
// the expansion of custom DAG-to-DAG patterns. // the expansion of custom DAG-to-DAG patterns.
@ -1939,7 +1939,7 @@ bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const {
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
for (unsigned i = 0; i != NumDefs; ++i) { for (unsigned i = 0; i != NumDefs; ++i) {
EVT VT = N->getValueType(i); MVT VT = N->getSimpleValueType(i);
if (!N->hasAnyUseOfValue(i)) if (!N->hasAnyUseOfValue(i))
continue; continue;
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
@ -1973,7 +1973,7 @@ int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
} }
for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG); for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
RegDefPos.IsValid(); RegDefPos.Advance()) { RegDefPos.IsValid(); RegDefPos.Advance()) {
EVT VT = RegDefPos.GetValue(); MVT VT = RegDefPos.GetValue();
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
if (RegPressure[RCId] >= RegLimit[RCId]) if (RegPressure[RCId] >= RegLimit[RCId])
++PDiff; ++PDiff;
@ -1986,7 +1986,7 @@ int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const {
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
for (unsigned i = 0; i != NumDefs; ++i) { for (unsigned i = 0; i != NumDefs; ++i) {
EVT VT = N->getValueType(i); MVT VT = N->getSimpleValueType(i);
if (!N->hasAnyUseOfValue(i)) if (!N->hasAnyUseOfValue(i))
continue; continue;
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
@ -2097,7 +2097,7 @@ void RegReductionPQBase::unscheduledNode(SUnit *SU) {
const SDNode *PN = PredSU->getNode(); const SDNode *PN = PredSU->getNode();
if (!PN->isMachineOpcode()) { if (!PN->isMachineOpcode()) {
if (PN->getOpcode() == ISD::CopyFromReg) { if (PN->getOpcode() == ISD::CopyFromReg) {
EVT VT = PN->getValueType(0); MVT VT = PN->getSimpleValueType(0);
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
} }
@ -2109,14 +2109,14 @@ void RegReductionPQBase::unscheduledNode(SUnit *SU) {
if (POpc == TargetOpcode::EXTRACT_SUBREG || if (POpc == TargetOpcode::EXTRACT_SUBREG ||
POpc == TargetOpcode::INSERT_SUBREG || POpc == TargetOpcode::INSERT_SUBREG ||
POpc == TargetOpcode::SUBREG_TO_REG) { POpc == TargetOpcode::SUBREG_TO_REG) {
EVT VT = PN->getValueType(0); MVT VT = PN->getSimpleValueType(0);
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
continue; continue;
} }
unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
for (unsigned i = 0; i != NumDefs; ++i) { for (unsigned i = 0; i != NumDefs; ++i) {
EVT VT = PN->getValueType(i); MVT VT = PN->getSimpleValueType(i);
if (!PN->hasAnyUseOfValue(i)) if (!PN->hasAnyUseOfValue(i))
continue; continue;
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
@ -2133,7 +2133,7 @@ void RegReductionPQBase::unscheduledNode(SUnit *SU) {
if (SU->NumSuccs && N->isMachineOpcode()) { if (SU->NumSuccs && N->isMachineOpcode()) {
unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i); MVT VT = N->getSimpleValueType(i);
if (VT == MVT::Glue || VT == MVT::Other) if (VT == MVT::Glue || VT == MVT::Other)
continue; continue;
if (!N->hasAnyUseOfValue(i)) if (!N->hasAnyUseOfValue(i))

2
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
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@ -562,7 +562,7 @@ void ScheduleDAGSDNodes::RegDefIter::Advance() {
for (;DefIdx < NodeNumDefs; ++DefIdx) { for (;DefIdx < NodeNumDefs; ++DefIdx) {
if (!Node->hasAnyUseOfValue(DefIdx)) if (!Node->hasAnyUseOfValue(DefIdx))
continue; continue;
ValueType = Node->getValueType(DefIdx); ValueType = Node->getSimpleValueType(DefIdx);
++DefIdx; ++DefIdx;
return; // Found a normal regdef. return; // Found a normal regdef.
} }

4
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
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@ -135,13 +135,13 @@ namespace llvm {
const SDNode *Node; const SDNode *Node;
unsigned DefIdx; unsigned DefIdx;
unsigned NodeNumDefs; unsigned NodeNumDefs;
EVT ValueType; MVT ValueType;
public: public:
RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD); RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
bool IsValid() const { return Node != NULL; } bool IsValid() const { return Node != NULL; }
EVT GetValue() const { MVT GetValue() const {
assert(IsValid() && "bad iterator"); assert(IsValid() && "bad iterator");
return ValueType; return ValueType;
} }