From 8617f3cf1498da31790360b33dc1d818ed339988 Mon Sep 17 00:00:00 2001
From: Duraid Madina <duraid@octopus.com.au>
Date: Thu, 22 Dec 2005 07:14:45 +0000
Subject: [PATCH] we can't do this directly in lowering, so we need this case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24951 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/IA64/IA64ISelDAGToDAG.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index c135f314e08..177365081fd 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -343,6 +343,14 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
 
   case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
   
+  case IA64ISD::GETFD: {
+    SDOperand Input = Select(N->getOperand(0));
+    SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag, Input);
+    CodeGenMap[Op.getValue(0)] = Result;
+    CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+    return Result.getValue(Op.ResNo);
+  } 
+  
   case ISD::CALL:
   case ISD::TAILCALL: { {
         // FIXME: This is a workaround for a bug in tblgen.