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This fixes one divergence between LLVM and binutils for ARM in the
text section. Assume the following bit of annotated assembly: .section .data.rel.ro,"aw",%progbits .align 2 .LAlpha: .long startval(GOTOFF) .text .align 2 .type main,%function .align 4 main: ;;; assume "main" starts at offset 0x20 0x0 push {r11, lr} 0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-4) + 8) = -20 0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-8) + 8) = -16 0xc ... blah .LBeta: 0x10 add r0, pc, r0 0x14 ... blah .LGamma: 0x18 add r1, pc, r1 Above snippet results in the following relocs in the .o file for the first pair of movw/movt instructions 00000024 R_ARM_MOVW_PREL_NC .LAlpha 00000028 R_ARM_MOVT_PREL .LAlpha And the encoded instructions in the .o file for main: must be 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20 28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16 However, llc (prior to this commit) generates the following sequence 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20 28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1 What has to happen in the ArmAsmBackend is that if the relocation is PC relative, the 16 bits encoded as part of movw and movt must be both addends, not addresses. It makes sense to encode addresses by right shifting the value by 16, but the result is incorrect for PIC. i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case. This change agrees with what GNU as does, and makes the PIC code run. MC/ARM/elf-movt.s covers this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -164,23 +164,25 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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case FK_Data_4:
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return Value;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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Value >>= 16;
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// Fallthrough
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case ARM::fixup_arm_movw_lo16:
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case ARM::fixup_arm_movt_hi16_pcrel:
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case ARM::fixup_arm_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned Lo12 = Value & 0x0FFF;
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assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
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"Out of range pc-relative fixup value!");
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// inst{19-16} = Hi4;
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// inst{11-0} = Lo12;
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Value = (Hi4 << 16) | (Lo12);
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return Value;
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}
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case ARM::fixup_t2_movt_hi16:
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case ARM::fixup_t2_movt_hi16_pcrel:
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Value >>= 16;
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// Fallthrough
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case ARM::fixup_t2_movw_lo16:
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case ARM::fixup_t2_movt_hi16_pcrel:
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case ARM::fixup_t2_movw_lo16_pcrel: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned i = (Value & 0x800) >> 11;
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@ -190,8 +192,9 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// inst{26} = i;
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// inst{14-12} = Mid3;
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// inst{7-0} = Lo8;
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assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
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"Out of range pc-relative fixup value!");
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Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
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uint64_t swapped = (Value & 0xFFFF0000) >> 16;
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swapped |= (Value & 0x0000FFFF) << 16;
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return swapped;
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@ -9,10 +9,10 @@
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barf: @ @barf
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@ BB#0: @ %entry
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movw r0, :lower16:GOT-(.LPC0_2+8)
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movt r0, :upper16:GOT-(.LPC0_2+16)
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movt r0, :upper16:GOT-(.LPC0_2+8)
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.LPC0_2:
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@ ASM: movw r0, :lower16:(GOT-(.LPC0_2+8))
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@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+16))
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@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8))
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@@ make sure that the text section fixups are sane too
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@ OBJ: '.text'
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@ -25,7 +25,7 @@ barf: @ @barf
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@ OBJ-NEXT: 'sh_info', 0x00000000
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@ OBJ-NEXT: 'sh_addralign', 0x00000004
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@ OBJ-NEXT: 'sh_entsize', 0x00000000
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@ OBJ-NEXT: '_section_data', 'f00f0fe3 ff0f4fe3'
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@ OBJ-NEXT: '_section_data', 'f00f0fe3 f40f4fe3'
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@ OBJ: Relocation 0x00000000
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@ OBJ-NEXT: 'r_offset', 0x00000000
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