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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Updating XTYPE/PRED intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228019 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
32a12b924e
commit
861e105e61
@ -1089,6 +1089,25 @@ def : T_P_pat <S2_vsathub_nopack, int_hexagon_S2_vsathub_nopack>;
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def : T_P_pat <S2_vsatwh_nopack, int_hexagon_S2_vsatwh_nopack>;
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def : T_P_pat <S2_vsatwuh_nopack, int_hexagon_S2_vsatwuh_nopack>;
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/********************************************************************
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* STYPE/PRED *
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*********************************************************************/
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// Predicate transfer
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def: Pat<(i32 (int_hexagon_C2_tfrpr (I32:$Rs))),
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(i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
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def: Pat<(i32 (int_hexagon_C2_tfrrp (I32:$Rs))),
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(i32 (C2_tfrpr (C2_tfrrp (I32:$Rs))))>;
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// Mask generate from predicate
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def: Pat<(i64 (int_hexagon_C2_mask (I32:$Rs))),
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(i64 (C2_mask (C2_tfrrp (I32:$Rs))))>;
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// Viterbi pack even and odd predicate bits
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def: Pat<(i32 (int_hexagon_C2_vitpack (I32:$Rs), (I32:$Rt))),
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(i32 (C2_vitpack (C2_tfrrp (I32:$Rs)),
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(C2_tfrrp (I32:$Rt))))>;
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/********************************************************************
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* STYPE/SHIFT *
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*********************************************************************/
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@ -1704,25 +1723,6 @@ class di_LDInstPI_diu4<string opc, Intrinsic IntID>
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[],
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"$src1 = $dst">;
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/********************************************************************
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* STYPE/PRED *
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*********************************************************************/
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// STYPE / PRED / Mask generate from predicate.
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def HEXAGON_C2_mask:
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di_SInst_qi <"mask", int_hexagon_C2_mask>;
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// STYPE / PRED / Predicate transfer.
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def HEXAGON_C2_tfrpr:
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si_SInst_qi <"", int_hexagon_C2_tfrpr>;
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def HEXAGON_C2_tfrrp:
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qi_SInst_si <"", int_hexagon_C2_tfrrp>;
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// STYPE / PRED / Viterbi pack even and odd predicate bits.
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def HEXAGON_C2_vitpack:
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si_SInst_qiqi <"vitpack",int_hexagon_C2_vitpack>;
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/********************************************************************
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* STYPE/VH *
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*********************************************************************/
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@ -78,6 +78,25 @@ def: T_RR_pat<C4_nbitsset, int_hexagon_C4_nbitsset>;
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def: T_RR_pat<C4_nbitsclr, int_hexagon_C4_nbitsclr>;
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def: T_RI_pat<C4_nbitsclri, int_hexagon_C4_nbitsclri>;
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class vcmpImm_pat <InstHexagon MI, Intrinsic IntID, PatLeaf immPred> :
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Pat <(IntID (i64 DoubleRegs:$src1), immPred:$src2),
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(MI (i64 DoubleRegs:$src1), immPred:$src2)>;
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def : vcmpImm_pat <A4_vcmpbeqi, int_hexagon_A4_vcmpbeqi, u8ImmPred>;
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def : vcmpImm_pat <A4_vcmpbgti, int_hexagon_A4_vcmpbgti, s8ImmPred>;
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def : vcmpImm_pat <A4_vcmpbgtui, int_hexagon_A4_vcmpbgtui, u7ImmPred>;
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def : vcmpImm_pat <A4_vcmpheqi, int_hexagon_A4_vcmpheqi, s8ImmPred>;
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def : vcmpImm_pat <A4_vcmphgti, int_hexagon_A4_vcmphgti, s8ImmPred>;
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def : vcmpImm_pat <A4_vcmphgtui, int_hexagon_A4_vcmphgtui, u7ImmPred>;
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def : vcmpImm_pat <A4_vcmpweqi, int_hexagon_A4_vcmpweqi, s8ImmPred>;
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def : vcmpImm_pat <A4_vcmpwgti, int_hexagon_A4_vcmpwgti, s8ImmPred>;
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def : vcmpImm_pat <A4_vcmpwgtui, int_hexagon_A4_vcmpwgtui, u7ImmPred>;
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def : T_PP_pat<A4_vcmpbeq_any, int_hexagon_A4_vcmpbeq_any>;
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def : T_RR_pat<A4_cmpbeq, int_hexagon_A4_cmpbeq>;
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def : T_RR_pat<A4_cmpbgt, int_hexagon_A4_cmpbgt>;
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def : T_RR_pat<A4_cmpbgtu, int_hexagon_A4_cmpbgtu>;
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@ -158,7 +158,7 @@ define i64 @C2_mask(i32 %a) {
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%z = call i64 @llvm.hexagon.C2.mask(i32 %a)
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ret i64 %z
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}
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; CHECK: = mask(r0)
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; CHECK: = mask(p0)
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; Check for TLB match
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declare i32 @llvm.hexagon.A4.tlbmatch(i64, i32)
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@ -196,3 +196,156 @@ define i32 @S4_ntstbit_r(i32 %a, i32 %b) {
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ret i32 %z
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}
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; CHECK: p0 = !tstbit(r0, r1)
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; Vector compare halfwords
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declare i32 @llvm.hexagon.A2.vcmpheq(i64, i64)
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define i32 @A2_vcmpheq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpheq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmphgt(i64, i64)
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define i32 @A2_vcmphgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmphgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmphgtu(i64, i64)
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define i32 @A2_vcmphgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmphgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpheqi(i64, i32)
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define i32 @A4_vcmpheqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpheqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmphgti(i64, i32)
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define i32 @A4_vcmphgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmphgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmphgtui(i64, i32)
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define i32 @A4_vcmphgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmphgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmph.gtu(r1:0, #0)
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; Vector compare bytes for any match
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declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64)
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define i32 @A4_vcmpbeq_any(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
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; Vector compare bytes
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declare i32 @llvm.hexagon.A2.vcmpbeq(i64, i64)
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define i32 @A2_vcmpbeq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpbeq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpbgtu(i64, i64)
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define i32 @A2_vcmpbgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpbgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpbgt(i64, i64)
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define i32 @A4_vcmpbgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpbeqi(i64, i32)
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define i32 @A4_vcmpbeqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbeqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpbgti(i64, i32)
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define i32 @A4_vcmpbgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpbgtui(i64, i32)
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define i32 @A4_vcmpbgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpbgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpb.gtu(r1:0, #0)
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; Vector compare words
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declare i32 @llvm.hexagon.A2.vcmpweq(i64, i64)
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define i32 @A2_vcmpweq(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpweq(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.eq(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpwgt(i64, i64)
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define i32 @A2_vcmpwgt(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpwgt(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gt(r1:0, r3:2)
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declare i32 @llvm.hexagon.A2.vcmpwgtu(i64, i64)
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define i32 @A2_vcmpwgtu(i64 %a, i64 %b) {
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%z = call i32 @llvm.hexagon.A2.vcmpwgtu(i64 %a, i64 %b)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gtu(r1:0, r3:2)
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declare i32 @llvm.hexagon.A4.vcmpweqi(i64, i32)
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define i32 @A4_vcmpweqi(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpweqi(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.eq(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpwgti(i64, i32)
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define i32 @A4_vcmpwgti(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpwgti(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gt(r1:0, #0)
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declare i32 @llvm.hexagon.A4.vcmpwgtui(i64, i32)
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define i32 @A4_vcmpwgtui(i64 %a) {
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%z = call i32 @llvm.hexagon.A4.vcmpwgtui(i64 %a, i32 0)
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ret i32 %z
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}
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; CHECK: p0 = vcmpw.gtu(r1:0, #0)
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; Viterbi pack even and odd predicate bitsclr
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declare i32 @llvm.hexagon.C2.vitpack(i32, i32)
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define i32 @C2_vitpack(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.C2.vitpack(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = vitpack(p1, p0)
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; Vector mux
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declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64)
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define i64 @C2_vmux(i32 %a, i64 %b, i64 %c) {
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%z = call i64 @llvm.hexagon.C2.vmux(i32 %a, i64 %b, i64 %c)
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ret i64 %z
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}
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; CHECK: = vmux(p0, r3:2, r5:4)
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