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https://github.com/c64scene-ar/llvm-6502.git
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[NVPTX] Add support for [SHL,SRA,SRL]_PARTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211936 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
10da1651ed
commit
863b0d45a5
@ -152,6 +152,13 @@ NVPTXTargetLowering::NVPTXTargetLowering(NVPTXTargetMachine &TM)
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32 , Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i32 , Custom);
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setOperationAction(ISD::SHL_PARTS, MVT::i64 , Custom);
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setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
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setOperationAction(ISD::SRL_PARTS, MVT::i64 , Custom);
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if (nvptxSubtarget.hasROT64()) {
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setOperationAction(ISD::ROTL, MVT::i64, Legal);
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setOperationAction(ISD::ROTR, MVT::i64, Legal);
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@ -345,6 +352,12 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "NVPTXISD::FUN_SHFL_CLAMP";
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case NVPTXISD::FUN_SHFR_CLAMP:
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return "NVPTXISD::FUN_SHFR_CLAMP";
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case NVPTXISD::IMAD:
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return "NVPTXISD::IMAD";
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case NVPTXISD::MUL_WIDE_SIGNED:
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return "NVPTXISD::MUL_WIDE_SIGNED";
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case NVPTXISD::MUL_WIDE_UNSIGNED:
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return "NVPTXISD::MUL_WIDE_UNSIGNED";
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case NVPTXISD::Tex1DFloatI32: return "NVPTXISD::Tex1DFloatI32";
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case NVPTXISD::Tex1DFloatFloat: return "NVPTXISD::Tex1DFloatFloat";
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case NVPTXISD::Tex1DFloatFloatLevel:
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@ -1279,6 +1292,127 @@ NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
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return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
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}
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/// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
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/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
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/// amount, or
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/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
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/// amount.
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SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getNumOperands() == 3 && "Not a double-shift!");
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assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
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EVT VT = Op.getValueType();
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unsigned VTBits = VT.getSizeInBits();
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SDLoc dl(Op);
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SDValue ShOpLo = Op.getOperand(0);
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SDValue ShOpHi = Op.getOperand(1);
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SDValue ShAmt = Op.getOperand(2);
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unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
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if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
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// For 32bit and sm35, we can use the funnel shift 'shf' instruction.
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// {dHi, dLo} = {aHi, aLo} >> Amt
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// dHi = aHi >> Amt
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// dLo = shf.r.clamp aLo, aHi, Amt
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SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
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SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
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ShAmt);
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SDValue Ops[2] = { Lo, Hi };
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return DAG.getMergeValues(Ops, dl);
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}
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else {
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// {dHi, dLo} = {aHi, aLo} >> Amt
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// - if (Amt>=size) then
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// dLo = aHi >> (Amt-size)
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// dHi = aHi >> Amt (this is either all 0 or all 1)
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// else
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// dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
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// dHi = aHi >> Amt
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SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant(VTBits, MVT::i32), ShAmt);
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SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
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SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
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DAG.getConstant(VTBits, MVT::i32));
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SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
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SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
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SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
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SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
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DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
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SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
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SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
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SDValue Ops[2] = { Lo, Hi };
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return DAG.getMergeValues(Ops, dl);
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}
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}
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/// LowerShiftLeftParts - Lower SHL_PARTS, which
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/// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
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/// amount, or
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/// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
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/// amount.
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SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Op.getNumOperands() == 3 && "Not a double-shift!");
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assert(Op.getOpcode() == ISD::SHL_PARTS);
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EVT VT = Op.getValueType();
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unsigned VTBits = VT.getSizeInBits();
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SDLoc dl(Op);
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SDValue ShOpLo = Op.getOperand(0);
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SDValue ShOpHi = Op.getOperand(1);
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SDValue ShAmt = Op.getOperand(2);
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if (VTBits == 32 && nvptxSubtarget.getSmVersion() >= 35) {
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// For 32bit and sm35, we can use the funnel shift 'shf' instruction.
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// {dHi, dLo} = {aHi, aLo} << Amt
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// dHi = shf.l.clamp aLo, aHi, Amt
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// dLo = aLo << Amt
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SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
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ShAmt);
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SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
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SDValue Ops[2] = { Lo, Hi };
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return DAG.getMergeValues(Ops, dl);
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}
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else {
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// {dHi, dLo} = {aHi, aLo} << Amt
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// - if (Amt>=size) then
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// dLo = aLo << Amt (all 0)
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// dLo = aLo << (Amt-size)
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// else
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// dLo = aLo << Amt
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// dHi = (aHi << Amt) | (aLo >> (size-Amt))
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SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
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DAG.getConstant(VTBits, MVT::i32), ShAmt);
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SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
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SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
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DAG.getConstant(VTBits, MVT::i32));
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SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
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SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
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SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
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SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
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DAG.getConstant(VTBits, MVT::i32), ISD::SETGE);
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SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
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SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
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SDValue Ops[2] = { Lo, Hi };
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return DAG.getMergeValues(Ops, dl);
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}
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}
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SDValue
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NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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@ -1299,6 +1433,11 @@ NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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return LowerSTORE(Op, DAG);
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case ISD::LOAD:
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return LowerLOAD(Op, DAG);
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case ISD::SHL_PARTS:
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return LowerShiftLeftParts(Op, DAG);
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case ISD::SRA_PARTS:
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case ISD::SRL_PARTS:
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return LowerShiftRightParts(Op, DAG);
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default:
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llvm_unreachable("Custom lowering not defined for operation");
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}
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@ -49,6 +49,8 @@ enum NodeType {
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CallSeqBegin,
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CallSeqEnd,
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CallPrototype,
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FUN_SHFL_CLAMP,
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FUN_SHFR_CLAMP,
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MUL_WIDE_SIGNED,
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MUL_WIDE_UNSIGNED,
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IMAD,
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@ -259,6 +261,9 @@ private:
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SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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@ -1364,6 +1364,32 @@ def : Pat<(i1 (select Int1Regs:$p, Int1Regs:$a, Int1Regs:$b)),
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(ORb1rr (ANDb1rr Int1Regs:$p, Int1Regs:$a),
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(ANDb1rr (NOT1 Int1Regs:$p), Int1Regs:$b))>;
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//
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// Funnnel shift in clamp mode
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//
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// - SDNodes are created so they can be used in the DAG code,
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// e.g. NVPTXISelLowering (LowerShiftLeftParts and LowerShiftRightParts)
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//
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def SDTIntShiftDOp: SDTypeProfile<1, 3,
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[SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
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SDTCisInt<0>, SDTCisInt<3>]>;
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def FUN_SHFL_CLAMP : SDNode<"NVPTXISD::FUN_SHFL_CLAMP", SDTIntShiftDOp, []>;
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def FUN_SHFR_CLAMP : SDNode<"NVPTXISD::FUN_SHFR_CLAMP", SDTIntShiftDOp, []>;
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def FUNSHFLCLAMP : NVPTXInst<(outs Int32Regs:$dst),
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(ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
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"shf.l.clamp.b32 \t$dst, $lo, $hi, $amt;",
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[(set Int32Regs:$dst,
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(FUN_SHFL_CLAMP Int32Regs:$lo,
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Int32Regs:$hi, Int32Regs:$amt))]>;
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def FUNSHFRCLAMP : NVPTXInst<(outs Int32Regs:$dst),
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(ins Int32Regs:$lo, Int32Regs:$hi, Int32Regs:$amt),
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"shf.r.clamp.b32 \t$dst, $lo, $hi, $amt;",
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[(set Int32Regs:$dst,
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(FUN_SHFR_CLAMP Int32Regs:$lo,
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Int32Regs:$hi, Int32Regs:$amt))]>;
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//-----------------------------------
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// Data Movement (Load / Store, Move)
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//-----------------------------------
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38
test/CodeGen/NVPTX/shift-parts.ll
Normal file
38
test/CodeGen/NVPTX/shift-parts.ll
Normal file
@ -0,0 +1,38 @@
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; CHECK: shift_parts_left_128
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define void @shift_parts_left_128(i128* %val, i128* %amtptr) {
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; CHECK: shl.b64
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; CHECK: mov.u32
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; CHECK: sub.s32
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; CHECK: shr.u64
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; CHECK: or.b64
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; CHECK: add.s32
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; CHECK: shl.b64
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; CHECK: setp.gt.s32
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; CHECK: selp.b64
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; CHECK: shl.b64
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%amt = load i128* %amtptr
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%a = load i128* %val
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%val0 = shl i128 %a, %amt
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store i128 %val0, i128* %val
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ret void
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}
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; CHECK: shift_parts_right_128
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define void @shift_parts_right_128(i128* %val, i128* %amtptr) {
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; CHECK: shr.u64
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; CHECK: sub.s32
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; CHECK: shl.b64
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; CHECK: or.b64
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; CHECK: add.s32
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; CHECK: shr.s64
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; CHECK: setp.gt.s32
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; CHECK: selp.b64
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; CHECK: shr.s64
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%amt = load i128* %amtptr
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%a = load i128* %val
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%val0 = ashr i128 %a, %amt
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store i128 %val0, i128* %val
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ret void
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}
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