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https://github.com/c64scene-ar/llvm-6502.git
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Change a whole bunch of code to be built around RegsForValue instead of
a single register number. This fully implements promotion for inline asms, expand is close but not quite right yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26316 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
4c1aa86657
commit
864635ad7b
@ -78,6 +78,43 @@ namespace {
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clEnumValEnd));
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} // namespace
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namespace {
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/// RegsForValue - This struct represents the physical registers that a
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/// particular value is assigned and the type information about the value.
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/// This is needed because values can be promoted into larger registers and
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/// expanded into multiple smaller registers than the value.
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struct RegsForValue {
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/// Regs - This list hold the register (for legal and promoted values)
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/// or register set (for expanded values) that the value should be assigned
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/// to.
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std::vector<unsigned> Regs;
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/// RegVT - The value type of each register.
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///
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MVT::ValueType RegVT;
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/// ValueVT - The value type of the LLVM value, which may be promoted from
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/// RegVT or made from merging the two expanded parts.
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MVT::ValueType ValueVT;
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RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
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RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
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: RegVT(regvt), ValueVT(valuevt) {
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Regs.push_back(Reg);
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}
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RegsForValue(const std::vector<unsigned> ®s,
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MVT::ValueType regvt, MVT::ValueType valuevt)
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: Regs(regs), RegVT(regvt), ValueVT(valuevt) {
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}
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/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
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/// this value and returns the result as a ValueVT value. This uses
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/// Chain/Flag as the input and updates them for the output Chain/Flag.
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SDOperand getCopyFromRegs(SelectionDAG &DAG,
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SDOperand &Chain, SDOperand &Flag);
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};
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}
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namespace llvm {
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//===--------------------------------------------------------------------===//
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@ -120,7 +157,7 @@ namespace llvm {
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}
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// If this value is represented with multiple target registers, make sure
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// to create enough consequtive registers of the right (smaller) type.
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// to create enough consecutive registers of the right (smaller) type.
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unsigned NT = VT-1; // Find the type to use.
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while (TLI.getNumElements((MVT::ValueType)NT) != 1)
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--NT;
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@ -412,11 +449,12 @@ public:
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return N = NewN;
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}
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unsigned GetAvailableRegister(bool OutReg, bool InReg,
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const std::vector<unsigned> &RegChoices,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs);
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RegsForValue GetRegistersForValue(const std::string &ConstrCode,
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MVT::ValueType VT,
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bool OutReg, bool InReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs);
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// Terminator instructions.
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void visitRet(ReturnInst &I);
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void visitBr(BranchInst &I);
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@ -1130,49 +1168,145 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
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DAG.setRoot(Result.second);
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}
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/// GetAvailableRegister - Pick a register from RegChoices that is available
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/// for input and/or output as specified by isOutReg/isInReg. If an allocatable
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/// register is found, it is returned and added to the specified set of used
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/// registers. If not, zero is returned.
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unsigned SelectionDAGLowering::
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GetAvailableRegister(bool isOutReg, bool isInReg,
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const std::vector<unsigned> &RegChoices,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs) {
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const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
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MachineFunction &MF = *CurMBB->getParent();
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for (unsigned i = 0, e = RegChoices.size(); i != e; ++i) {
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unsigned Reg = RegChoices[i];
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// See if this register is available.
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if (isOutReg && OutputRegs.count(Reg)) continue; // Already used.
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if (isInReg && InputRegs.count(Reg)) continue; // Already used.
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SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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SDOperand &Chain, SDOperand &Flag) {
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SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
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Chain = Val.getValue(1);
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Flag = Val.getValue(2);
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// If the result was expanded, copy from the top part.
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if (Regs.size() > 1) {
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assert(Regs.size() == 2 &&
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"Cannot expand to more than 2 elts yet!");
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SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
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Chain = Val.getValue(1);
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Flag = Val.getValue(2);
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return DAG.getNode(ISD::MERGE_VALUES, ValueVT, Val, Hi);
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}
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// Check to see if this register is allocatable (i.e. don't give out the
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// stack pointer).
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bool Found = false;
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for (MRegisterInfo::regclass_iterator RC = MRI->regclass_begin(),
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E = MRI->regclass_end(); !Found && RC != E; ++RC) {
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// NOTE: This isn't ideal. In particular, this might allocate the
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// frame pointer in functions that need it (due to them not being taken
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// out of allocation, because a variable sized allocation hasn't been seen
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// yet). This is a slight code pessimization, but should still work.
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for (TargetRegisterClass::iterator I = (*RC)->allocation_order_begin(MF),
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E = (*RC)->allocation_order_end(MF); I != E; ++I)
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if (*I == Reg) {
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Found = true;
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break;
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}
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}
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if (!Found) continue;
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// Okay, this register is good, return it.
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if (isOutReg) OutputRegs.insert(Reg); // Mark used.
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if (isInReg) InputRegs.insert(Reg); // Mark used.
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return Reg;
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// Otherwise, if the return value was promoted, truncate it to the
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// appropriate type.
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if (RegVT == ValueVT)
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return Val;
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if (MVT::isInteger(RegVT))
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return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
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else
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return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
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}
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/// isAllocatableRegister - If the specified register is safe to allocate,
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/// i.e. it isn't a stack pointer or some other special register, return the
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/// register class for the register. Otherwise, return null.
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static const TargetRegisterClass *
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isAllocatableRegister(unsigned Reg, MachineFunction &MF,
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const MRegisterInfo *MRI) {
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for (MRegisterInfo::regclass_iterator RC = MRI->regclass_begin(),
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E = MRI->regclass_end(); RC != E; ++RC) {
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// NOTE: This isn't ideal. In particular, this might allocate the
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// frame pointer in functions that need it (due to them not being taken
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// out of allocation, because a variable sized allocation hasn't been seen
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// yet). This is a slight code pessimization, but should still work.
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for (TargetRegisterClass::iterator I = (*RC)->allocation_order_begin(MF),
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E = (*RC)->allocation_order_end(MF); I != E; ++I)
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if (*I == Reg)
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return *RC;
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}
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return 0;
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}
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RegsForValue SelectionDAGLowering::
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GetRegistersForValue(const std::string &ConstrCode,
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MVT::ValueType VT, bool isOutReg, bool isInReg,
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std::set<unsigned> &OutputRegs,
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std::set<unsigned> &InputRegs) {
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
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std::vector<unsigned> Regs;
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unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
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MVT::ValueType RegVT;
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MVT::ValueType ValueVT = VT;
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if (PhysReg.first) {
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if (VT == MVT::Other)
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ValueVT = *PhysReg.second->vt_begin();
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RegVT = VT;
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// This is a explicit reference to a physical register.
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Regs.push_back(PhysReg.first);
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// If this is an expanded reference, add the rest of the regs to Regs.
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if (NumRegs != 1) {
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RegVT = *PhysReg.second->vt_begin();
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TargetRegisterClass::iterator I = PhysReg.second->begin();
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TargetRegisterClass::iterator E = PhysReg.second->end();
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for (; *I != PhysReg.first; ++I)
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assert(I != E && "Didn't find reg!");
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// Already added the first reg.
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--NumRegs; ++I;
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for (; NumRegs; --NumRegs, ++I) {
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assert(I != E && "Ran out of registers to allocate!");
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Regs.push_back(*I);
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}
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}
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return RegsForValue(Regs, RegVT, ValueVT);
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}
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// This is a reference to a register class. Allocate NumRegs consecutive,
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// available, registers from the class.
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std::vector<unsigned> RegClassRegs =
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TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
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const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
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MachineFunction &MF = *CurMBB->getParent();
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unsigned NumAllocated = 0;
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for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
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unsigned Reg = RegClassRegs[i];
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// See if this register is available.
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if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
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(isInReg && InputRegs.count(Reg))) { // Already used.
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Check to see if this register is allocatable (i.e. don't give out the
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// stack pointer).
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const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, MRI);
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if (!RC) {
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// Make sure we find consecutive registers.
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NumAllocated = 0;
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continue;
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}
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// Okay, this register is good, we can use it.
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++NumAllocated;
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// If we allocated enough consecutive
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if (NumAllocated == NumRegs) {
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unsigned RegStart = (i-NumAllocated)+1;
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unsigned RegEnd = i+1;
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// Mark all of the allocated registers used.
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for (unsigned i = RegStart; i != RegEnd; ++i) {
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unsigned Reg = RegClassRegs[i];
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Regs.push_back(Reg);
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if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
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if (isInReg) InputRegs.insert(Reg); // Mark reg used.
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}
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return RegsForValue(Regs, *RC->vt_begin(), VT);
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}
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}
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// Otherwise, we couldn't allocate enough registers for this.
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return RegsForValue();
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}
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/// visitInlineAsm - Handle a call to an InlineAsm object.
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///
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void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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@ -1235,39 +1369,40 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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ConstraintVTs.push_back(OpVT);
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std::pair<unsigned, const TargetRegisterClass*> Reg =
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TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT);
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if (Reg.first == 0) continue; // Not assigned a fixed reg.
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unsigned TheReg = Reg.first;
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if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
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continue; // Not assigned a fixed reg.
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// FIXME: Handle expanded physreg refs!
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// Build a list of regs that this operand uses. This always has a single
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// element for promoted/expanded operands.
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RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
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false, false,
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OutputRegs, InputRegs);
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switch (Constraints[i].Type) {
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case InlineAsm::isOutput:
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// We can't assign any other output to this register.
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OutputRegs.insert(TheReg);
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OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
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// If this is an early-clobber output, it cannot be assigned to the same
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// value as the input reg.
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if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
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InputRegs.insert(TheReg);
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InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
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break;
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case InlineAsm::isInput:
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// We can't assign any other input to this register.
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InputRegs.insert(TheReg);
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InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
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break;
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case InlineAsm::isClobber:
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// Clobbered regs cannot be used as inputs or outputs.
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InputRegs.insert(TheReg);
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OutputRegs.insert(TheReg);
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InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
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OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
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break;
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}
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}
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// Loop over all of the inputs, copying the operand values into the
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// appropriate registers and processing the output regs.
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unsigned RetValReg = 0;
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std::vector<std::pair<unsigned, Value*> > IndirectStoresToEmit;
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bool FoundOutputConstraint = false;
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RegsForValue RetValRegs;
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std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
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OpNum = 1;
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for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
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@ -1276,58 +1411,47 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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switch (Constraints[i].Type) {
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case InlineAsm::isOutput: {
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// Copy the output from the appropriate register. Find a regsister that
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// If this is an early-clobber output, or if there is an input
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// constraint that matches this, we need to reserve the input register
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// so no other inputs allocate to it.
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bool UsesInputRegister = false;
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if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
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UsesInputRegister = true;
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// Copy the output from the appropriate register. Find a register that
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// we can use.
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// Check to see if this is a physreg reference.
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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TLI.getRegForInlineAsmConstraint(ConstraintCode, ConstraintVTs[i]);
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unsigned DestReg;
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if (PhysReg.first)
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DestReg = PhysReg.first;
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else {
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std::vector<unsigned> Regs =
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TLI.getRegClassForInlineAsmConstraint(ConstraintCode,
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ConstraintVTs[i]);
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RegsForValue Regs =
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GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
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true, UsesInputRegister,
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OutputRegs, InputRegs);
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assert(!Regs.Regs.empty() && "Couldn't allocate output reg!");
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// If this is an early-clobber output, or if there is an input
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// constraint that matches this, we need to reserve the input register
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// so no other inputs allocate to it.
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bool UsesInputRegister = false;
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if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
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UsesInputRegister = true;
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DestReg = GetAvailableRegister(true, UsesInputRegister,
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Regs, OutputRegs, InputRegs);
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}
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assert(DestReg && "Couldn't allocate output reg!");
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const Type *OpTy;
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if (!Constraints[i].isIndirectOutput) {
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assert(!FoundOutputConstraint &&
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assert(RetValRegs.Regs.empty() &&
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"Cannot have multiple output constraints yet!");
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FoundOutputConstraint = true;
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assert(I.getType() != Type::VoidTy && "Bad inline asm!");
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RetValReg = DestReg;
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RetValRegs = Regs;
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} else {
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Value *CallOperand = I.getOperand(OpNum);
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IndirectStoresToEmit.push_back(std::make_pair(DestReg, CallOperand));
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IndirectStoresToEmit.push_back(std::make_pair(Regs, CallOperand));
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OpNum++; // Consumes a call operand.
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}
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// Add information to the INLINEASM node to know that this register is
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// set.
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AsmNodeOperands.push_back(DAG.getRegister(DestReg, ConstraintVTs[i]));
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AsmNodeOperands.push_back(DAG.getConstant(2, MVT::i32)); // ISDEF
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// FIXME:
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// FIXME: Handle multiple regs here.
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// FIXME:
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unsigned DestReg = Regs.Regs[0];
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AsmNodeOperands.push_back(DAG.getRegister(DestReg, Regs.RegVT));
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AsmNodeOperands.push_back(DAG.getConstant(2, MVT::i32)); // ISDEF
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break;
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}
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case InlineAsm::isInput: {
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Value *CallOperand = I.getOperand(OpNum);
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OpNum++; // Consumes a call operand.
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unsigned SrcReg;
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SDOperand ResOp;
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unsigned ResOpType;
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SDOperand InOperandVal = getValue(CallOperand);
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@ -1336,6 +1460,7 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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// If this is required to match an output register we have already set,
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// just use its register.
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unsigned OperandNo = atoi(ConstraintCode.c_str());
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unsigned SrcReg;
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SrcReg = cast<RegisterSDNode>(AsmNodeOperands[OperandNo*2+2])->getReg();
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ResOp = DAG.getRegister(SrcReg, ConstraintVTs[i]);
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ResOpType = 1;
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@ -1343,39 +1468,46 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
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Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
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Flag = Chain.getValue(1);
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} else {
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TargetLowering::ConstraintType CTy = TargetLowering::C_Register;
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TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
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if (ConstraintCode.size() == 1) // not a physreg name.
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CTy = TLI.getConstraintType(ConstraintCode[0]);
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switch (CTy) {
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default: assert(0 && "Unknown constraint type! FAIL!");
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case TargetLowering::C_Register: {
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std::pair<unsigned, const TargetRegisterClass*> PhysReg =
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TLI.getRegForInlineAsmConstraint(ConstraintCode, ConstraintVTs[i]);
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// FIXME: should be match fail.
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assert(PhysReg.first && "Unknown physical register name!");
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SrcReg = PhysReg.first;
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Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
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Flag = Chain.getValue(1);
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ResOp = DAG.getRegister(SrcReg, ConstraintVTs[i]);
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ResOpType = 1;
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break;
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}
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||||
case TargetLowering::C_RegisterClass: {
|
||||
// Copy the input into the appropriate register.
|
||||
std::vector<unsigned> Regs =
|
||||
TLI.getRegClassForInlineAsmConstraint(ConstraintCode,
|
||||
ConstraintVTs[i]);
|
||||
SrcReg = GetAvailableRegister(false, true, Regs,
|
||||
OutputRegs, InputRegs);
|
||||
// Copy the input into the appropriate registers.
|
||||
RegsForValue InRegs =
|
||||
GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
|
||||
false, true, OutputRegs, InputRegs);
|
||||
// FIXME: should be match fail.
|
||||
assert(SrcReg && "Wasn't able to allocate register!");
|
||||
Chain = DAG.getCopyToReg(Chain, SrcReg, InOperandVal, Flag);
|
||||
Flag = Chain.getValue(1);
|
||||
assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
|
||||
|
||||
if (InRegs.Regs.size() == 1) {
|
||||
// If there is a single register and the types differ, this must be
|
||||
// a promotion.
|
||||
if (InRegs.RegVT != InRegs.ValueVT) {
|
||||
if (MVT::isInteger(InRegs.RegVT))
|
||||
InOperandVal = DAG.getNode(ISD::ANY_EXTEND, InRegs.RegVT,
|
||||
InOperandVal);
|
||||
else
|
||||
InOperandVal = DAG.getNode(ISD::FP_EXTEND, InRegs.RegVT,
|
||||
InOperandVal);
|
||||
}
|
||||
Chain = DAG.getCopyToReg(Chain, InRegs.Regs[0], InOperandVal, Flag);
|
||||
Flag = Chain.getValue(1);
|
||||
|
||||
ResOp = DAG.getRegister(InRegs.Regs[0], InRegs.RegVT);
|
||||
} else {
|
||||
for (unsigned i = 0, e = InRegs.Regs.size(); i != e; ++i) {
|
||||
SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, InRegs.RegVT,
|
||||
InOperandVal,
|
||||
DAG.getConstant(i, MVT::i32));
|
||||
Chain = DAG.getCopyToReg(Chain, InRegs.Regs[i], Part, Flag);
|
||||
Flag = Chain.getValue(1);
|
||||
}
|
||||
ResOp = DAG.getRegister(InRegs.Regs[0], InRegs.RegVT);
|
||||
}
|
||||
|
||||
ResOp = DAG.getRegister(SrcReg, ConstraintVTs[i]);
|
||||
ResOpType = 1;
|
||||
break;
|
||||
}
|
||||
@ -1411,26 +1543,18 @@ void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
|
||||
|
||||
// If this asm returns a register value, copy the result from that register
|
||||
// and set it as the value of the call.
|
||||
if (RetValReg) {
|
||||
SDOperand Val = DAG.getCopyFromReg(Chain, RetValReg,
|
||||
TLI.getValueType(I.getType()), Flag);
|
||||
Chain = Val.getValue(1);
|
||||
Flag = Val.getValue(2);
|
||||
setValue(&I, Val);
|
||||
}
|
||||
if (!RetValRegs.Regs.empty())
|
||||
setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
|
||||
|
||||
std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
|
||||
|
||||
// Process indirect outputs, first output all of the flagged copies out of
|
||||
// physregs.
|
||||
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
|
||||
RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
|
||||
Value *Ptr = IndirectStoresToEmit[i].second;
|
||||
const Type *Ty = cast<PointerType>(Ptr->getType())->getElementType();
|
||||
SDOperand Val = DAG.getCopyFromReg(Chain, IndirectStoresToEmit[i].first,
|
||||
TLI.getValueType(Ty), Flag);
|
||||
Chain = Val.getValue(1);
|
||||
Flag = Val.getValue(2);
|
||||
StoresToEmit.push_back(std::make_pair(Val, Ptr));
|
||||
SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
|
||||
StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
|
||||
}
|
||||
|
||||
// Emit the non-flagged stores from the physregs.
|
||||
@ -1689,8 +1813,8 @@ void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
|
||||
SDOperand Value = getMemsetValue(Op2, VT, DAG);
|
||||
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, getRoot(),
|
||||
Value,
|
||||
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
|
||||
DAG.getSrcValue(I.getOperand(1), Offset));
|
||||
getMemBasePlusOffset(Op1, Offset, DAG, TLI),
|
||||
DAG.getSrcValue(I.getOperand(1), Offset));
|
||||
OutChains.push_back(Store);
|
||||
Offset += VTSize;
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user