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Add X86 code emitter support AVX encoded MRMDestReg instructions.

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Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2013-03-16 03:44:31 +00:00
parent e0c489d22b
commit 8647750dfb
4 changed files with 94 additions and 32 deletions
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lib/Target/X86/X86CodeEmitter.cpp
+15 -4
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@@ -1047,9 +1047,15 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags,
// MRMDestReg instructions forms:
// dst(ModR/M), src(ModR/M)
// dst(ModR/M), src(ModR/M), imm8
if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
// dst(ModR/M), src1(VEX_4V), src2(ModR/M)
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_B = 0x0;
if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg()))
CurOp++;
if (HasVEX_4V)
VEX_4V = getVEXRegisterEncoding(MI, CurOp++);
if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
VEX_R = 0x0;
break;
case X86II::MRM0r: case X86II::MRM1r:
@@ -1284,9 +1290,14 @@ void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI,
case X86II::MRMDestReg: {
MCE.emitByte(BaseOpcode);
unsigned SrcRegNum = CurOp+1;
if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
SrcRegNum++;
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
CurOp += 2;
getX86RegNum(MI.getOperand(SrcRegNum).getReg()));
CurOp = SrcRegNum + 1;
break;
}
case X86II::MRMDestMem: {