mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-22 10:24:26 +00:00
Fix coding style violations. Remove white spaces and tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
@ -334,17 +334,17 @@ EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
|
||||
// Lo0: initial value of Lo register
|
||||
// Hi0: initial value of Hi register
|
||||
// Return true if pattern matching was successful.
|
||||
static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
|
||||
static bool SelectMadd(SDNode *ADDENode, SelectionDAG *CurDAG) {
|
||||
// ADDENode's second operand must be a flag output of an ADDC node in order
|
||||
// for the matching to be successful.
|
||||
SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
|
||||
SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
|
||||
|
||||
if (ADDCNode->getOpcode() != ISD::ADDC)
|
||||
return false;
|
||||
|
||||
SDValue MultHi = ADDENode->getOperand(0);
|
||||
SDValue MultLo = ADDCNode->getOperand(0);
|
||||
SDNode* MultNode = MultHi.getNode();
|
||||
SDNode *MultNode = MultHi.getNode();
|
||||
unsigned MultOpc = MultHi.getOpcode();
|
||||
|
||||
// MultHi and MultLo must be generated by the same node,
|
||||
@ -407,17 +407,17 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
|
||||
// Lo0: initial value of Lo register
|
||||
// Hi0: initial value of Hi register
|
||||
// Return true if pattern matching was successful.
|
||||
static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
|
||||
static bool SelectMsub(SDNode *SUBENode, SelectionDAG *CurDAG) {
|
||||
// SUBENode's second operand must be a flag output of an SUBC node in order
|
||||
// for the matching to be successful.
|
||||
SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
|
||||
SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
|
||||
|
||||
if (SUBCNode->getOpcode() != ISD::SUBC)
|
||||
return false;
|
||||
|
||||
SDValue MultHi = SUBENode->getOperand(1);
|
||||
SDValue MultLo = SUBCNode->getOperand(1);
|
||||
SDNode* MultNode = MultHi.getNode();
|
||||
SDNode *MultNode = MultHi.getNode();
|
||||
unsigned MultOpc = MultHi.getOpcode();
|
||||
|
||||
// MultHi and MultLo must be generated by the same node,
|
||||
@ -472,9 +472,9 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
|
||||
return true;
|
||||
}
|
||||
|
||||
static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
if (DCI.isBeforeLegalize())
|
||||
return SDValue();
|
||||
|
||||
@ -485,9 +485,9 @@ static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
if (DCI.isBeforeLegalize())
|
||||
return SDValue();
|
||||
|
||||
@ -498,9 +498,9 @@ static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
if (DCI.isBeforeLegalizeOps())
|
||||
return SDValue();
|
||||
|
||||
@ -575,7 +575,7 @@ static bool InvertFPCondCode(Mips::CondCode CC) {
|
||||
|
||||
// Creates and returns an FPCmp node from a setcc node.
|
||||
// Returns Op if setcc is not a floating point comparison.
|
||||
static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
|
||||
static SDValue CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) {
|
||||
// must be a SETCC node
|
||||
if (Op.getOpcode() != ISD::SETCC)
|
||||
return Op;
|
||||
@ -597,7 +597,7 @@ static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
|
||||
}
|
||||
|
||||
// Creates and returns a CMovFPT/F node.
|
||||
static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
|
||||
static SDValue CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
|
||||
SDValue False, DebugLoc DL) {
|
||||
bool invert = InvertFPCondCode((Mips::CondCode)
|
||||
cast<ConstantSDNode>(Cond.getOperand(2))
|
||||
@ -607,9 +607,9 @@ static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
|
||||
True.getValueType(), True, False, Cond);
|
||||
}
|
||||
|
||||
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
if (DCI.isBeforeLegalizeOps())
|
||||
return SDValue();
|
||||
|
||||
@ -633,16 +633,16 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
|
||||
const DebugLoc DL = N->getDebugLoc();
|
||||
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
|
||||
SDValue True = N->getOperand(1);
|
||||
|
||||
|
||||
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
|
||||
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
|
||||
|
||||
|
||||
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
|
||||
}
|
||||
|
||||
static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformANDCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
// Pattern match EXT.
|
||||
// $dst = and ((sra or srl) $src , pos), (2**size - 1)
|
||||
// => ext $dst, $src, size, pos
|
||||
@ -680,9 +680,9 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
|
||||
DAG.getConstant(SMSize, MVT::i32));
|
||||
}
|
||||
|
||||
static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformORCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
// Pattern match INS.
|
||||
// $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
|
||||
// where mask1 = (2**size - 1) << pos, mask0 = ~mask1
|
||||
@ -734,9 +734,9 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
|
||||
DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
|
||||
}
|
||||
|
||||
static SDValue PerformADDCombine(SDNode *N, SelectionDAG& DAG,
|
||||
static SDValue PerformADDCombine(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const MipsSubtarget* Subtarget) {
|
||||
const MipsSubtarget *Subtarget) {
|
||||
// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
|
||||
|
||||
if (DCI.isBeforeLegalizeOps())
|
||||
@ -776,7 +776,7 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
|
||||
case ISD::UDIVREM:
|
||||
return PerformDivRemCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::SELECT:
|
||||
return PerformSELECTCombine(N, DAG, DCI, Subtarget);
|
||||
return PerformSELECTCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::AND:
|
||||
return PerformANDCombine(N, DAG, DCI, Subtarget);
|
||||
case ISD::OR:
|
||||
@ -847,7 +847,7 @@ static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
|
||||
/*
|
||||
static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
|
||||
DebugLoc dl,
|
||||
const MipsSubtarget* Subtarget,
|
||||
const MipsSubtarget *Subtarget,
|
||||
const TargetInstrInfo *TII,
|
||||
bool isFPCmp, unsigned Opc) {
|
||||
// There is no need to expand CMov instructions if target has
|
||||
@ -2011,7 +2011,7 @@ LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
// TODO: set SType according to the desired memory barrier behavior.
|
||||
SDValue
|
||||
MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
|
||||
MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const {
|
||||
unsigned SType = 0;
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
|
||||
@ -2019,7 +2019,7 @@ MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
|
||||
}
|
||||
|
||||
SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
|
||||
SelectionDAG& DAG) const {
|
||||
SelectionDAG &DAG) const {
|
||||
// FIXME: Need pseudo-fence for 'singlethread' fences
|
||||
// FIXME: Set SType for weaker fences where supported/appropriate.
|
||||
unsigned SType = 0;
|
||||
@ -2029,7 +2029,7 @@ SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
|
||||
}
|
||||
|
||||
SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
|
||||
SelectionDAG& DAG) const {
|
||||
SelectionDAG &DAG) const {
|
||||
DebugLoc DL = Op.getDebugLoc();
|
||||
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
|
||||
SDValue Shamt = Op.getOperand(2);
|
||||
@ -2051,15 +2051,15 @@ SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
|
||||
SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
|
||||
SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
|
||||
DAG.getConstant(0x20, MVT::i32));
|
||||
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, DAG.getConstant(0, MVT::i32),
|
||||
ShiftLeftLo);
|
||||
Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
|
||||
DAG.getConstant(0, MVT::i32), ShiftLeftLo);
|
||||
Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
|
||||
|
||||
SDValue Ops[2] = {Lo, Hi};
|
||||
return DAG.getMergeValues(Ops, 2, DL);
|
||||
}
|
||||
|
||||
SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
|
||||
SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
|
||||
bool IsSRA) const {
|
||||
DebugLoc DL = Op.getDebugLoc();
|
||||
SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
|
||||
@ -2425,10 +2425,10 @@ static unsigned getNextIntArgReg(unsigned Reg) {
|
||||
// Write ByVal Arg to arg registers and stack.
|
||||
static void
|
||||
WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
||||
SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
|
||||
SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
|
||||
SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
|
||||
SmallVector<SDValue, 8> &MemOpChains, int &LastFI,
|
||||
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
|
||||
MVT PtrType, bool isLittle) {
|
||||
unsigned LocMemOffset = VA.getLocMemOffset();
|
||||
unsigned Offset = 0;
|
||||
@ -2516,10 +2516,10 @@ WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
||||
// Copy Mips64 byVal arg to registers and stack.
|
||||
void static
|
||||
PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
||||
SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
|
||||
SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
|
||||
SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass,
|
||||
SmallVector<SDValue, 8> &MemOpChains, int &LastFI,
|
||||
MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
|
||||
EVT PtrTy, bool isLittle) {
|
||||
unsigned ByValSize = Flags.getByValSize();
|
||||
unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
|
||||
@ -2913,7 +2913,7 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
||||
// Assign locations to each value returned by this call.
|
||||
SmallVector<CCValAssign, 16> RVLocs;
|
||||
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
||||
getTargetMachine(), RVLocs, *DAG.getContext());
|
||||
getTargetMachine(), RVLocs, *DAG.getContext());
|
||||
|
||||
CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
|
||||
|
||||
@ -2932,9 +2932,9 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
||||
// Formal Arguments Calling Convention Implementation
|
||||
//===----------------------------------------------------------------------===//
|
||||
static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
|
||||
std::vector<SDValue>& OutChains,
|
||||
std::vector<SDValue> &OutChains,
|
||||
SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
|
||||
const Argument *FuncArg) {
|
||||
unsigned LocMem = VA.getLocMemOffset();
|
||||
unsigned FirstWord = LocMem / 4;
|
||||
@ -2959,8 +2959,8 @@ static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
|
||||
// Create frame object on stack and copy registers used for byval passing to it.
|
||||
static unsigned
|
||||
CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
|
||||
std::vector<SDValue>& OutChains, SelectionDAG &DAG,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
|
||||
std::vector<SDValue> &OutChains, SelectionDAG &DAG,
|
||||
const CCValAssign &VA, const ISD::ArgFlagsTy &Flags,
|
||||
MachineFrameInfo *MFI, bool IsRegLoc,
|
||||
SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
|
||||
EVT PtrTy, const Argument *FuncArg) {
|
||||
@ -3207,7 +3207,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
|
||||
|
||||
// CCState - Info about the registers and stack slot.
|
||||
CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
|
||||
getTargetMachine(), RVLocs, *DAG.getContext());
|
||||
getTargetMachine(), RVLocs, *DAG.getContext());
|
||||
|
||||
// Analize return values.
|
||||
CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
|
||||
|
||||
Reference in New Issue
Block a user