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Add some more "get address into register" code and a more TODOs/FIXMEs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111860 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-23 23:14:31 +00:00
parent 7fe55b739c
commit 8654c71e56
1 changed files with 22 additions and 0 deletions
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22
lib/Target/ARM/ARMFastISel.cpp
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@ -361,10 +361,32 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
unsigned Reg; unsigned Reg;
int Offset; int Offset;
// TODO: Think about using loadRegFromStackSlot() here when we can.
// See if we can handle this as Reg + Offset // See if we can handle this as Reg + Offset
if (!ARMComputeRegOffset(I, Reg, Offset)) if (!ARMComputeRegOffset(I, Reg, Offset))
return false; return false;
// Since the offset may be too large for the load instruction
// get the reg+offset into a register.
// TODO: Optimize this somewhat.
// FIXME: There is more than one register class in the world...
unsigned ScratchReg
= FuncInfo.MF->getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
ARMCC::CondCodes Pred = ARMCC::AL;
unsigned PredReg = 0;
if (!AFI->isThumbFunction())
emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
ScratchReg, Reg, Offset, Pred, PredReg,
static_cast<const ARMBaseInstrInfo&>(TII));
else {
assert(AFI->isThumb2Function());
emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
ScratchReg, Reg, Offset, Pred, PredReg,
static_cast<const ARMBaseInstrInfo&>(TII));
}
unsigned ResultReg = createResultReg(ARM::GPRRegisterClass); unsigned ResultReg = createResultReg(ARM::GPRRegisterClass);
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDR), ResultReg) TII.get(ARM::LDR), ResultReg)