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Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).

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Some assemblers can't recognize the aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25494 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-01-21 02:55:41 +00:00
parent a9c2091cd3
commit 86556a5f42
3 changed files with 9 additions and 9 deletions
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4
lib/Target/X86/X86FloatingPoint.cpp
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@ -324,11 +324,11 @@ static const TableEntry OpcodeTable[] = {
{ X86::FpADD32m , X86::FADD32m }, { X86::FpADD32m , X86::FADD32m },
{ X86::FpADD64m , X86::FADD64m }, { X86::FpADD64m , X86::FADD64m },
{ X86::FpCHS , X86::FCHS }, { X86::FpCHS , X86::FCHS },
{ X86::FpCMOVA , X86::FCMOVA },
{ X86::FpCMOVAE , X86::FCMOVAE },
{ X86::FpCMOVB , X86::FCMOVB }, { X86::FpCMOVB , X86::FCMOVB },
{ X86::FpCMOVBE , X86::FCMOVBE }, { X86::FpCMOVBE , X86::FCMOVBE },
{ X86::FpCMOVE , X86::FCMOVE }, { X86::FpCMOVE , X86::FCMOVE },
{ X86::FpCMOVNB , X86::FCMOVNB },
{ X86::FpCMOVNBE , X86::FCMOVNBE },
{ X86::FpCMOVNE , X86::FCMOVNE }, { X86::FpCMOVNE , X86::FCMOVNE },
{ X86::FpCMOVNP , X86::FCMOVNP }, { X86::FpCMOVNP , X86::FCMOVNP },
{ X86::FpCMOVP , X86::FCMOVP }, { X86::FpCMOVP , X86::FCMOVP },

2
lib/Target/X86/X86ISelPattern.cpp
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@ -758,7 +758,7 @@ void ISel::EmitSelectCC(SDOperand Cond, SDOperand True, SDOperand False,
static const unsigned CMOVTABFP[] = { static const unsigned CMOVTABFP[] = {
X86::FpCMOVE, X86::FpCMOVNE, /*missing*/0, /*missing*/0, X86::FpCMOVE, X86::FpCMOVNE, /*missing*/0, /*missing*/0,
/*missing*/0, /*missing*/ 0, X86::FpCMOVB, X86::FpCMOVBE, /*missing*/0, /*missing*/ 0, X86::FpCMOVB, X86::FpCMOVBE,
X86::FpCMOVA, X86::FpCMOVAE, X86::FpCMOVP, X86::FpCMOVNP X86::FpCMOVNBE,X86::FpCMOVNB, X86::FpCMOVP, X86::FpCMOVNP
}; };
static const int SSE_CMOVTAB[] = { static const int SSE_CMOVTAB[] = {
/*CMPEQ*/ 0, /*CMPNEQ*/ 4, /*missing*/ 0, /*missing*/ 0, /*CMPEQ*/ 0, /*CMPNEQ*/ 4, /*missing*/ 0, /*missing*/ 0,

12
lib/Target/X86/X86InstrInfo.td
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@ -2862,10 +2862,10 @@ let isTwoAddress = 1 in {
def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, def FpCMOVP : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_P, STATUS))]>; X86_COND_P, STATUS))]>;
def FpCMOVAE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, def FpCMOVNB : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_AE, STATUS))]>; X86_COND_AE, STATUS))]>;
def FpCMOVA : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, def FpCMOVNBE: FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
[(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2, [(set RFP:$dst, (X86cmov RFP:$src1, RFP:$src2,
X86_COND_A, STATUS))]>; X86_COND_A, STATUS))]>;
def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP, def FpCMOVNE : FpI<(ops RFP:$dst, RFP:$src1, RFP:$src2), CondMovFP,
@ -2884,10 +2884,10 @@ def FCMOVE : FPI<0xC8, AddRegFrm, (ops RST:$op),
"fcmove {$op, %ST(0)|%ST(0), $op}">, DA; "fcmove {$op, %ST(0)|%ST(0), $op}">, DA;
def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op), def FCMOVP : FPI<0xD8, AddRegFrm, (ops RST:$op),
"fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA;
def FCMOVAE : FPI<0xC0, AddRegFrm, (ops RST:$op), def FCMOVNB : FPI<0xC0, AddRegFrm, (ops RST:$op),
"fcmovae {$op, %ST(0)|%ST(0), $op}">, DB; "fcmovnb {$op, %ST(0)|%ST(0), $op}">, DB;
def FCMOVA : FPI<0xD0, AddRegFrm, (ops RST:$op), def FCMOVNBE : FPI<0xD0, AddRegFrm, (ops RST:$op),
"fcmova {$op, %ST(0)|%ST(0), $op}">, DB; "fcmovnbe {$op, %ST(0)|%ST(0), $op}">, DB;
def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op), def FCMOVNE : FPI<0xC8, AddRegFrm, (ops RST:$op),
"fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB;
def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op), def FCMOVNP : FPI<0xD8, AddRegFrm, (ops RST:$op),