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Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they

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can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107097 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-28 23:40:25 +00:00
parent 45e01d2751
commit 8674949513
2 changed files with 12 additions and 1 deletions
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3
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -2322,7 +2322,8 @@ SDValue DAGCombiner::visitOR(SDNode *N) {
} }
// fold (or x, undef) -> -1 // fold (or x, undef) -> -1
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { if (!LegalOperations &&
(N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
} }

10
test/CodeGen/ARM/2010-06-28-DAGCombineUndef.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llc < %s -march=arm -mattr=+neon
define void @main() nounwind {
entry:
store <2 x i64> undef, <2 x i64>* undef, align 16
%0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
%1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
store <16 x i8> %1, <16 x i8>* undef, align 16
ret void
}