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fsel can take a different FP type for the comparison and for the result. As such

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split the FSEL family into 4 things instead of just two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-10-02 06:58:23 +00:00
parent 7c0d664c21
commit 867940d1b7
3 changed files with 37 additions and 22 deletions
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19
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -752,18 +752,21 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
CodeGenMap[Op.getValue(1)] = Result.getValue(1); CodeGenMap[Op.getValue(1)] = Result.getValue(1);
return SDOperand(Result.Val, Op.ResNo); return SDOperand(Result.Val, Op.ResNo);
} }
case PPCISD::FSEL: case PPCISD::FSEL: {
if (N->getValueType(0) == MVT::f32) unsigned Opc;
CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32, if (N->getValueType(0) == MVT::f32) {
Select(N->getOperand(0)), Opc = N->getOperand(0).getValueType() == MVT::f32 ?
Select(N->getOperand(1)), PPC::FSELSS : PPC::FSELSD;
Select(N->getOperand(2))); } else {
else Opc = N->getOperand(0).getValueType() == MVT::f64 ?
CurDAG->SelectNodeTo(N, PPC::FSELD, MVT::f64, PPC::FSELDD : PPC::FSELDS;
}
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
Select(N->getOperand(0)), Select(N->getOperand(0)),
Select(N->getOperand(1)), Select(N->getOperand(1)),
Select(N->getOperand(2))); Select(N->getOperand(2)));
return SDOperand(N, 0); return SDOperand(N, 0);
}
case PPCISD::FCFID: case PPCISD::FCFID:
CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0), CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
Select(N->getOperand(0))); Select(N->getOperand(0)));

7
lib/Target/PowerPC/PPCISelPattern.cpp
View File

@ -816,9 +816,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
Tmp2 = SelectExpr(N.getOperand(1)); Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2)); Tmp3 = SelectExpr(N.getOperand(2));
if (N.getOperand(0).getValueType() == MVT::f32) if (N.getOperand(0).getValueType() == MVT::f32)
BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); Opc = N.getOperand(0).getValueType() == MVT::f32 ?
PPC::FSELSS : PPC::FSELSD;
else else
BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); Opc = N.getOperand(0).getValueType() == MVT::f64 ?
PPC::FSELDD : PPC::FSELDS;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result; return Result;
case PPCISD::FCFID: case PPCISD::FCFID:
Tmp1 = SelectExpr(N.getOperand(0)); Tmp1 = SelectExpr(N.getOperand(0));

15
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -791,15 +791,24 @@ def FNMSUBS : AForm_1<59, 30,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fnmsubs $FRT, $FRA, $FRC, $FRB", "fnmsubs $FRT, $FRA, $FRC, $FRB",
[]>; []>;
// FSEL is artificially split into 4 and 8-byte forms. // FSEL is artificially split into 4 and 8-byte forms for the comparison type
def FSELD : AForm_1<63, 23, // and 4/8 byte forms for the result and operand type..
def FSELDD : AForm_1<63, 23,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB), (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", "fsel $FRT, $FRA, $FRC, $FRB",
[]>; []>;
def FSELS : AForm_1<63, 23, def FSELSS : AForm_1<63, 23,
(ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB), (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB", "fsel $FRT, $FRA, $FRC, $FRB",
[]>; []>;
def FSELDS : AForm_1<63, 23, // result Double, comparison Single
(ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FSELSD : AForm_1<63, 23, // result Single, comparison Double
(ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
"fsel $FRT, $FRA, $FRC, $FRB",
[]>;
def FADD : AForm_2<63, 21, def FADD : AForm_2<63, 21,
(ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB), (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
"fadd $FRT, $FRA, $FRB", "fadd $FRT, $FRA, $FRB",