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llvm-build: Fill in some details w.r.t. component's parents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143624 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -37,6 +37,15 @@ class ComponentInfo(object):
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# under.
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# under.
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self.parent = parent
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self.parent = parent
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# The parent instance, once loaded.
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self.parent_instance = None
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self.children = []
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def set_parent_instance(self, parent):
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assert parent.name == self.parent, "Unexpected parent!"
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self.parent_instance = parent
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self.parent_instance.children.append(self)
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def get_component_references(self):
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def get_component_references(self):
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"""get_component_references() -> iter
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"""get_component_references() -> iter
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@ -54,6 +54,12 @@ class LLVMProjectInfo(object):
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ci.name, ci.subpath, existing.subpath))
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ci.name, ci.subpath, existing.subpath))
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self.component_info_map[ci.name] = ci
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self.component_info_map[ci.name] = ci
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# Add the root component, which does not go in any list.
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if '$ROOT' in self.component_info_map:
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fatal("project is not allowed to define $ROOT component")
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self.component_info_map['$ROOT'] = componentinfo.GroupComponentInfo(
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'/', '$ROOT', None)
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# Topologically order the component information according to their
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# Topologically order the component information according to their
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# component references.
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# component references.
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def visit_component_info(ci, current_stack, current_set):
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def visit_component_info(ci, current_stack, current_set):
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@ -73,6 +79,13 @@ class LLVMProjectInfo(object):
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# Otherwise, mark the component info as visited and traverse.
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# Otherwise, mark the component info as visited and traverse.
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components_to_visit.remove(ci)
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components_to_visit.remove(ci)
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# Validate the parent reference, which we treat specially.
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parent = self.component_info_map.get(ci.parent)
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if parent is None:
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fatal("component %r has invalid reference %r (via %r)" % (
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ci.name, ci.parent, 'parent'))
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ci.set_parent_instance(parent)
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for relation,referent_name in ci.get_component_references():
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for relation,referent_name in ci.get_component_references():
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# Validate that the reference is ok.
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# Validate that the reference is ok.
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referent = self.component_info_map.get(referent_name)
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referent = self.component_info_map.get(referent_name)
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@ -90,6 +103,11 @@ class LLVMProjectInfo(object):
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# Finally, add the component info to the ordered list.
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# Finally, add the component info to the ordered list.
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self.ordered_component_infos.append(ci)
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self.ordered_component_infos.append(ci)
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# FIXME: We aren't actually correctly checking for cycles along the
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# parent edges. Haven't decided how I want to handle this -- I thought
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# about only checking cycles by relation type. If we do that, it falls
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# out easily. If we don't, we should special case the check.
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self.ordered_component_infos = []
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self.ordered_component_infos = []
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components_to_visit = set(component_infos)
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components_to_visit = set(component_infos)
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while components_to_visit:
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while components_to_visit:
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