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Avoid creating chain dependencies from CopyToReg nodes to load and store

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nodes. This doesn't currently have much impact the generated code, but it
does produce simpler-looking SelectionDAGs, and consequently
simpler-looking ScheduleDAGs, because there are fewer spurious
dependencies.

In particular, CopyValueToVirtualRegister now uses the entry node as the
input chain dependency for new CopyToReg nodes instead of calling getRoot
and depending on the most recent memory reference.

Also, rename UnorderedChains to PendingExports and pull it up from being
a local variable in SelectionDAGISel::BuildSelectionDAG to being a
member variable of SelectionDAGISel, so that it doesn't have to be
passed around to all the places that need it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48893 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2008-03-27 19:56:19 +00:00
parent 4a3c0ac798
commit 86e1ebf9bb
2 changed files with 73 additions and 56 deletions
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3
include/llvm/CodeGen/SelectionDAGISel.h
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@@ -182,8 +182,7 @@ private:
std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
FunctionLoweringInfo &FuncInfo);
void CodeGenAndEmitDAG(SelectionDAG &DAG);
void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
std::vector<SDOperand> &UnorderedChains);
void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.