6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-24 22:24:54 +00:00
Code Issues Projects Releases Wiki Activity

[mips][msa] Added missing check in performSRACombine

Browse Source 
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2013-09-27 09:25:29 +00:00
parent 6b4fa2256c
commit 86f309b4d1
2 changed files with 141 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/Mips/MipsSEISelLowering.cpp
View File

@@ -609,6 +609,10 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
if (!ShAmount)
return SDValue();
if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
return SDValue();
EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();