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ARM assembly parsing support for RSB instruction.

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Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-21 22:37:43 +00:00
parent 616fbdf987
commit 86fdff0fa7
3 changed files with 71 additions and 3 deletions
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14
lib/Target/ARM/ARMInstrInfo.td
View File

@ -4256,3 +4256,17 @@ def : InstAlias<"push${p} $regs",
(STMDB_UPD SP, pred:$p, reglist:$regs)>;
def : InstAlias<"pop${p} $regs",
(LDMIA_UPD SP, pred:$p, reglist:$regs)>;
// RSB two-operand forms (optional explicit destination operand)
def : InstAlias<"rsb${s}${p} $Rdn, $imm",
(RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
Requires<[IsARM]>;
def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
(RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
Requires<[IsARM]>;
def : InstAlias<"rsb${s}${p} $Rdn, $shift",
(RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
cc_out:$s)>, Requires<[IsARM]>;
def : InstAlias<"rsb${s}${p} $Rdn, $shift",
(RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
cc_out:$s)>, Requires<[IsARM]>;

3
test/MC/ARM/arm_instructions.s
View File

@ -57,9 +57,6 @@
@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
mvns r1,r2
@ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0]
rsb r1,r2,r3
@ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0]
rsc r1,r2,r3

57
test/MC/ARM/basic-arm-instructions.s
View File

@ -1108,6 +1108,63 @@ _func:
@ CHECK: revshne r9, r1 @ encoding: [0xb1,0x9f,0xff,0x16]
@------------------------------------------------------------------------------
@ RSB
@------------------------------------------------------------------------------
rsb r4, r5, #0xf000
rsb r4, r5, r6
rsb r4, r5, r6, lsl #5
rsblo r4, r5, r6, lsr #5
rsb r4, r5, r6, lsr #5
rsb r4, r5, r6, asr #5
rsb r4, r5, r6, ror #5
rsb r6, r7, r8, lsl r9
rsb r6, r7, r8, lsr r9
rsb r6, r7, r8, asr r9
rsble r6, r7, r8, ror r9
rsb r4, r5, r6, rrx
@ destination register is optional
rsb r5, #0xf000
rsb r4, r5
rsb r4, r5, lsl #5
rsb r4, r5, lsr #5
rsbne r4, r5, lsr #5
rsb r4, r5, asr #5
rsb r4, r5, ror #5
rsbgt r6, r7, lsl r9
rsb r6, r7, lsr r9
rsb r6, r7, asr r9
rsb r6, r7, ror r9
rsb r4, r5, rrx
@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2]
@ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0]
@ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0]
@ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30]
@ CHECK: rsb r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0xe0]
@ CHECK: rsb r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x65,0xe0]
@ CHECK: rsb r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x65,0xe0]
@ CHECK: rsb r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x67,0xe0]
@ CHECK: rsb r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x67,0xe0]
@ CHECK: rsb r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x67,0xe0]
@ CHECK: rsble r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x67,0xd0]
@ CHECK: rsb r4, r5, r6, rrx @ encoding: [0x66,0x40,0x65,0xe0]
@ CHECK: rsb r5, r5, #61440 @ encoding: [0x0f,0x5a,0x65,0xe2]
@ CHECK: rsb r4, r4, r5 @ encoding: [0x05,0x40,0x64,0xe0]
@ CHECK: rsb r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x64,0xe0]
@ CHECK: rsb r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0xe0]
@ CHECK: rsbne r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x64,0x10]
@ CHECK: rsb r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x64,0xe0]
@ CHECK: rsb r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x64,0xe0]
@ CHECK: rsbgt r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x66,0xc0]
@ CHECK: rsb r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x66,0xe0]
@ CHECK: rsb r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x66,0xe0]
@ CHECK: rsb r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x66,0xe0]
@ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0]
@------------------------------------------------------------------------------
@ STM*
@------------------------------------------------------------------------------