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https://github.com/c64scene-ar/llvm-6502.git
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ARM VLD1 single lane assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
204aa64f30
commit
872eedbb3a
@ -1994,7 +1994,7 @@ class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
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// VFP/NEON Instruction aliases for type suffices.
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class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result> :
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InstAlias<!strconcat(opc, dt, asm), Result>;
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InstAlias<!strconcat(opc, dt, "\t", asm), Result>;
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multiclass VFPDT8ReqInstAlias<string opc, string asm, dag Result> {
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def I8 : VFPDataTypeInstAlias<opc, ".i8", asm, Result>;
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def S8 : VFPDataTypeInstAlias<opc, ".s8", asm, Result>;
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@ -2071,7 +2071,7 @@ multiclass VFPDTAnyNoF64InstAlias<string opc, string asm, dag Result> {
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// above, as we care about the ultimate instruction enum names generated, unlike
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// for instalias defs.
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class NEONDataTypeAsmPseudoInst<string opc, string dt, string asm, dag iops> :
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AsmPseudoInst<!strconcat(opc, dt, asm), iops>, Requires<[HasNEON]>;
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AsmPseudoInst<!strconcat(opc, dt, "\t", asm), iops>, Requires<[HasNEON]>;
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multiclass NEONDT8ReqAsmPseudoInst<string opc, string asm, dag iops> {
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def I8 : NEONDataTypeAsmPseudoInst<opc, ".i8", asm, iops>;
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def S8 : NEONDataTypeAsmPseudoInst<opc, ".s8", asm, iops>;
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@ -5593,11 +5593,30 @@ defm : VFPDT16ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
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defm : VFPDT32ReqInstAlias<"vtrn${p}", "$Qd, $Qm",
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(VTRNq32 QPR:$Qd, QPR:$Qm, pred:$p)>;
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// FIXME: Proof of concept pseudos. We want to parameterize these for all
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// the suffices we have to support.
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// VLD1 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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defm VLD1LNdWB_register_Asm :
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NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
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(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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@ -4754,16 +4754,48 @@ validateInstruction(MCInst &Inst,
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static unsigned getRealVLDNOpcode(unsigned Opc) {
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switch(Opc) {
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default: assert(0 && "unexpected opcode!");
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case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_P8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_I8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_S8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_U8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_P16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_I16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_S16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_U16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_F: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_F32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_I32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_S32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_fixed_Asm_U32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_P8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_I8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_S8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_U8: return ARM::VLD1LNd8_UPD;
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case ARM::VLD1LNdWB_register_Asm_16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_P16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_I16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_S16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_U16: return ARM::VLD1LNd16_UPD;
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case ARM::VLD1LNdWB_register_Asm_32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_F: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_F32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_I32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_S32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdWB_register_Asm_U32: return ARM::VLD1LNd32_UPD;
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case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8;
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case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
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case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32;
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case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32;
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case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32;
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@ -4778,6 +4810,70 @@ processInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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// Handle NEON VLD1 complex aliases.
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case ARM::VLD1LNdWB_register_Asm_8:
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case ARM::VLD1LNdWB_register_Asm_P8:
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case ARM::VLD1LNdWB_register_Asm_I8:
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case ARM::VLD1LNdWB_register_Asm_S8:
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case ARM::VLD1LNdWB_register_Asm_U8:
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case ARM::VLD1LNdWB_register_Asm_16:
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case ARM::VLD1LNdWB_register_Asm_P16:
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case ARM::VLD1LNdWB_register_Asm_I16:
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case ARM::VLD1LNdWB_register_Asm_S16:
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case ARM::VLD1LNdWB_register_Asm_U16:
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case ARM::VLD1LNdWB_register_Asm_32:
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case ARM::VLD1LNdWB_register_Asm_F:
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case ARM::VLD1LNdWB_register_Asm_F32:
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case ARM::VLD1LNdWB_register_Asm_I32:
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case ARM::VLD1LNdWB_register_Asm_S32:
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case ARM::VLD1LNdWB_register_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(Inst.getOperand(4)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(5)); // CondCode
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TmpInst.addOperand(Inst.getOperand(6));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD1LNdWB_fixed_Asm_8:
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case ARM::VLD1LNdWB_fixed_Asm_P8:
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case ARM::VLD1LNdWB_fixed_Asm_I8:
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case ARM::VLD1LNdWB_fixed_Asm_S8:
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case ARM::VLD1LNdWB_fixed_Asm_U8:
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case ARM::VLD1LNdWB_fixed_Asm_16:
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case ARM::VLD1LNdWB_fixed_Asm_P16:
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case ARM::VLD1LNdWB_fixed_Asm_I16:
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case ARM::VLD1LNdWB_fixed_Asm_S16:
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case ARM::VLD1LNdWB_fixed_Asm_U16:
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case ARM::VLD1LNdWB_fixed_Asm_32:
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case ARM::VLD1LNdWB_fixed_Asm_F:
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case ARM::VLD1LNdWB_fixed_Asm_F32:
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case ARM::VLD1LNdWB_fixed_Asm_I32:
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case ARM::VLD1LNdWB_fixed_Asm_S32:
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case ARM::VLD1LNdWB_fixed_Asm_U32: {
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MCInst TmpInst;
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// Shuffle the operands around so the lane index operand is in the
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// right place.
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TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
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TmpInst.addOperand(Inst.getOperand(2)); // Rn
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TmpInst.addOperand(Inst.getOperand(3)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
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TmpInst.addOperand(Inst.getOperand(1)); // lane
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD1LNdAsm_8:
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case ARM::VLD1LNdAsm_P8:
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case ARM::VLD1LNdAsm_I8:
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