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elimiante use of getNode that takes vector of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29612 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -157,7 +157,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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unsigned CallOpc = ARMISD::CALL;
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if (InFlag.Val)
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Ops.push_back(InFlag);
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Chain = DAG.getNode(CallOpc, NodeTys, Ops);
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Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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std::vector<SDOperand> ResultVals;
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@ -182,7 +182,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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return Chain;
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ResultVals.push_back(Chain);
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SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
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SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
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ResultVals.size());
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return Res.getValue(Op.ResNo);
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}
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@ -279,7 +280,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
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}
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SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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