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[DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.

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Allows more aggressive folding of ashr/shl pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2015-06-26 14:51:49 +00:00
parent 3791d56da6
commit 875007d3c4
2 changed files with 17 additions and 4 deletions
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11
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -771,10 +771,13 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits)
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Op.getOperand(0),
Op.getOperand(1)));
if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
SDNodeFlags Flags;
Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
return TLO.CombineTo(Op,
TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
Op.getOperand(1), &Flags));
}
int Log2 = NewMask.exactLogBase2();
if (Log2 >= 0) {