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Code Issues Projects Releases Wiki Activity

Nuke the old JIT.

Browse Source 
I am sure we will be finding bits and pieces of dead code for years to
come, but this is a good start.

Thanks to Lang Hames for making MCJIT a good replacement!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215111 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
2014-08-07 14:21:18 +00:00
parent 7ad7c75048
commit 875710a2fd
224 changed files with 177 additions and 12478 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/Sparc/CMakeLists.txt
View File

@@ -2,9 +2,8 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td)
tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info)
tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter)
tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel)
@@ -24,8 +23,6 @@ add_llvm_target(SparcCodeGen
SparcSubtarget.cpp
SparcTargetMachine.cpp
SparcSelectionDAGInfo.cpp
SparcJITInfo.cpp
SparcCodeEmitter.cpp
SparcMCInstLower.cpp
SparcTargetObjectFile.cpp
)

2
lib/Target/Sparc/Makefile
View File

@@ -16,7 +16,7 @@ BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \
SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \
SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \
SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \
SparcGenCodeEmitter.inc SparcGenMCCodeEmitter.inc
SparcGenMCCodeEmitter.inc
DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc

2
lib/Target/Sparc/Sparc.h
View File

@@ -29,8 +29,6 @@ namespace llvm {
FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
FunctionPass *createSparcJITCodeEmitterPass(SparcTargetMachine &TM,
JITCodeEmitter &JCE);
void LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
MCInst &OutMI,

281
lib/Target/Sparc/SparcCodeEmitter.cpp
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@@ -1,281 +0,0 @@
//===-- Sparc/SparcCodeEmitter.cpp - Convert Sparc Code to Machine Code ---===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===---------------------------------------------------------------------===//
//
// This file contains the pass that transforms the Sparc machine instructions
// into relocatable machine code.
//
//===---------------------------------------------------------------------===//
#include "Sparc.h"
#include "MCTargetDesc/SparcMCExpr.h"
#include "SparcRelocations.h"
#include "SparcTargetMachine.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
#define DEBUG_TYPE "jit"
STATISTIC(NumEmitted, "Number of machine instructions emitted");
namespace {
class SparcCodeEmitter : public MachineFunctionPass {
SparcJITInfo *JTI;
const SparcInstrInfo *II;
const DataLayout *TD;
const SparcSubtarget *Subtarget;
TargetMachine &TM;
JITCodeEmitter &MCE;
const std::vector<MachineConstantPoolEntry> *MCPEs;
bool IsPIC;
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo> ();
MachineFunctionPass::getAnalysisUsage(AU);
}
static char ID;
public:
SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
: MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr),
TM(tm), MCE(mce), MCPEs(nullptr),
IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override {
return "Sparc Machine Code Emitter";
}
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
void emitInstruction(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB);
private:
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const;
unsigned getCallTargetOpValue(const MachineInstr &MI,
unsigned) const;
unsigned getBranchTargetOpValue(const MachineInstr &MI,
unsigned) const;
unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
unsigned) const;
unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
unsigned) const;
void emitWord(unsigned Word);
unsigned getRelocation(const MachineInstr &MI,
const MachineOperand &MO) const;
void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc) const;
void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const;
};
} // end anonymous namespace.
char SparcCodeEmitter::ID = 0;
bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
SparcTargetMachine &Target = static_cast<SparcTargetMachine &>(
const_cast<TargetMachine &>(MF.getTarget()));
JTI = Target.getSubtargetImpl()->getJITInfo();
II = Target.getSubtargetImpl()->getInstrInfo();
TD = Target.getSubtargetImpl()->getDataLayout();
Subtarget = &TM.getSubtarget<SparcSubtarget>();
MCPEs = &MF.getConstantPool()->getConstants();
JTI->Initialize(MF, IsPIC);
MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ());
do {
DEBUG(errs() << "JITTing function '"
<< MF.getName() << "'\n");
MCE.startFunction(MF);
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
MBB != E; ++MBB){
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
E = MBB->instr_end(); I != E;)
emitInstruction(*I++, *MBB);
}
} while (MCE.finishFunction(MF));
return false;
}
void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI,
MachineBasicBlock &MBB) {
DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI);
MCE.processDebugLoc(MI->getDebugLoc(), true);
++NumEmitted;
switch (MI->getOpcode()) {
default: {
emitWord(getBinaryCodeForInstr(*MI));
break;
}
case TargetOpcode::INLINEASM: {
// We allow inline assembler nodes with empty bodies - they can
// implicitly define registers, which is ok for JIT.
if (MI->getOperand(0).getSymbolName()[0]) {
report_fatal_error("JIT does not support inline asm!");
}
break;
}
case TargetOpcode::CFI_INSTRUCTION:
break;
case TargetOpcode::EH_LABEL: {
MCE.emitLabel(MI->getOperand(0).getMCSymbol());
break;
}
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL: {
// Do nothing.
break;
}
case SP::GETPCX: {
report_fatal_error("JIT does not support pseudo instruction GETPCX yet!");
break;
}
}
MCE.processDebugLoc(MI->getDebugLoc(), false);
}
void SparcCodeEmitter::emitWord(unsigned Word) {
DEBUG(errs() << " 0x";
errs().write_hex(Word) << "\n");
MCE.emitWordBE(Word);
}
/// getMachineOpValue - Return binary encoding of operand. If the machine
/// operand requires relocation, record the relocation and return zero.
unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const {
if (MO.isReg())
return TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(
MO.getReg());
else if (MO.isImm())
return static_cast<unsigned>(MO.getImm());
else if (MO.isGlobal())
emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO));
else if (MO.isSymbol())
emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
else if (MO.isCPI())
emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));
else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
else
llvm_unreachable("Unable to encode MachineOperand!");
return 0;
}
unsigned SparcCodeEmitter::getCallTargetOpValue(const MachineInstr &MI,
unsigned opIdx) const {
const MachineOperand MO = MI.getOperand(opIdx);
return getMachineOpValue(MI, MO);
}
unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI,
unsigned opIdx) const {
const MachineOperand MO = MI.getOperand(opIdx);
return getMachineOpValue(MI, MO);
}
unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
unsigned opIdx) const {
const MachineOperand MO = MI.getOperand(opIdx);
return getMachineOpValue(MI, MO);
}
unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
unsigned opIdx) const {
const MachineOperand MO = MI.getOperand(opIdx);
return getMachineOpValue(MI, MO);
}
unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
const MachineOperand &MO) const {
unsigned TF = MO.getTargetFlags();
switch (TF) {
default:
case SparcMCExpr::VK_Sparc_None: break;
case SparcMCExpr::VK_Sparc_LO: return SP::reloc_sparc_lo;
case SparcMCExpr::VK_Sparc_HI: return SP::reloc_sparc_hi;
case SparcMCExpr::VK_Sparc_H44: return SP::reloc_sparc_h44;
case SparcMCExpr::VK_Sparc_M44: return SP::reloc_sparc_m44;
case SparcMCExpr::VK_Sparc_L44: return SP::reloc_sparc_l44;
case SparcMCExpr::VK_Sparc_HH: return SP::reloc_sparc_hh;
case SparcMCExpr::VK_Sparc_HM: return SP::reloc_sparc_hm;
}
unsigned Opc = MI.getOpcode();
switch (Opc) {
default: break;
case SP::CALL: return SP::reloc_sparc_pc30;
case SP::BA:
case SP::BCOND:
case SP::FBCOND: return SP::reloc_sparc_pc22;
case SP::BPXCC: return SP::reloc_sparc_pc19;
}
llvm_unreachable("unknown reloc!");
}
void SparcCodeEmitter::emitGlobalAddress(const GlobalValue *GV,
unsigned Reloc) const {
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
const_cast<GlobalValue *>(GV), 0,
true));
}
void SparcCodeEmitter::
emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, ES, 0, 0));
}
void SparcCodeEmitter::
emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, CPI, 0, false));
}
void SparcCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
unsigned Reloc) const {
MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Reloc, BB));
}
/// createSparcJITCodeEmitterPass - Return a pass that emits the collected Sparc
/// code to the specified MCE object.
FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM,
JITCodeEmitter &JCE) {
return new SparcCodeEmitter(TM, JCE);
}
#include "SparcGenCodeEmitter.inc"

326
lib/Target/Sparc/SparcJITInfo.cpp
View File

@@ -1,326 +0,0 @@
//===-- SparcJITInfo.cpp - Implement the Sparc JIT Interface --------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the Sparc target.
//
//===----------------------------------------------------------------------===//
#include "SparcJITInfo.h"
#include "Sparc.h"
#include "SparcRelocations.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/JITCodeEmitter.h"
#include "llvm/Support/Memory.h"
using namespace llvm;
#define DEBUG_TYPE "jit"
/// JITCompilerFunction - This contains the address of the JIT function used to
/// compile a function lazily.
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
extern "C" void SparcCompilationCallback();
extern "C" {
#if defined (__sparc__)
#if defined(__arch64__)
#define FRAME_PTR(X) #X "+2047"
#else
#define FRAME_PTR(X) #X
#endif
asm(
".text\n"
"\t.align 4\n"
"\t.global SparcCompilationCallback\n"
"\t.type SparcCompilationCallback, #function\n"
"SparcCompilationCallback:\n"
// Save current register window and create stack.
// 128 (save area) + 6*8 (for arguments) + 16*8 (for float regfile) = 304
"\tsave %sp, -304, %sp\n"
// save float regfile to the stack.
"\tstd %f0, [" FRAME_PTR(%fp) "-0]\n"
"\tstd %f2, [" FRAME_PTR(%fp) "-8]\n"
"\tstd %f4, [" FRAME_PTR(%fp) "-16]\n"
"\tstd %f6, [" FRAME_PTR(%fp) "-24]\n"
"\tstd %f8, [" FRAME_PTR(%fp) "-32]\n"
"\tstd %f10, [" FRAME_PTR(%fp) "-40]\n"
"\tstd %f12, [" FRAME_PTR(%fp) "-48]\n"
"\tstd %f14, [" FRAME_PTR(%fp) "-56]\n"
"\tstd %f16, [" FRAME_PTR(%fp) "-64]\n"
"\tstd %f18, [" FRAME_PTR(%fp) "-72]\n"
"\tstd %f20, [" FRAME_PTR(%fp) "-80]\n"
"\tstd %f22, [" FRAME_PTR(%fp) "-88]\n"
"\tstd %f24, [" FRAME_PTR(%fp) "-96]\n"
"\tstd %f26, [" FRAME_PTR(%fp) "-104]\n"
"\tstd %f28, [" FRAME_PTR(%fp) "-112]\n"
"\tstd %f30, [" FRAME_PTR(%fp) "-120]\n"
// stubaddr is in %g1.
"\tcall SparcCompilationCallbackC\n"
"\t mov %g1, %o0\n"
// restore float regfile from the stack.
"\tldd [" FRAME_PTR(%fp) "-0], %f0\n"
"\tldd [" FRAME_PTR(%fp) "-8], %f2\n"
"\tldd [" FRAME_PTR(%fp) "-16], %f4\n"
"\tldd [" FRAME_PTR(%fp) "-24], %f6\n"
"\tldd [" FRAME_PTR(%fp) "-32], %f8\n"
"\tldd [" FRAME_PTR(%fp) "-40], %f10\n"
"\tldd [" FRAME_PTR(%fp) "-48], %f12\n"
"\tldd [" FRAME_PTR(%fp) "-56], %f14\n"
"\tldd [" FRAME_PTR(%fp) "-64], %f16\n"
"\tldd [" FRAME_PTR(%fp) "-72], %f18\n"
"\tldd [" FRAME_PTR(%fp) "-80], %f20\n"
"\tldd [" FRAME_PTR(%fp) "-88], %f22\n"
"\tldd [" FRAME_PTR(%fp) "-96], %f24\n"
"\tldd [" FRAME_PTR(%fp) "-104], %f26\n"
"\tldd [" FRAME_PTR(%fp) "-112], %f28\n"
"\tldd [" FRAME_PTR(%fp) "-120], %f30\n"
// restore original register window and
// copy %o0 to %g1
"\trestore %o0, 0, %g1\n"
// call the new stub
"\tjmp %g1\n"
"\t nop\n"
"\t.size SparcCompilationCallback, .-SparcCompilationCallback"
);
#else
void SparcCompilationCallback() {
llvm_unreachable(
"Cannot call SparcCompilationCallback() on a non-sparc arch!");
}
#endif
}
#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))
#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define NOP_INST SETHI_INST(0, 0)
#define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
| ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F))
#define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19) \
| (5 << 14))
#define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \
| ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F))
#define SUB_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x04 << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define XOR_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x03 << 19) \
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
#define BA_INST(tgt) (0x10800000 | ((tgt) & 0x3FFFFF))
// Emit instructions to jump to Addr and store the starting address of
// the instructions emitted in the scratch register.
static void emitInstrForIndirectJump(intptr_t Addr,
unsigned scratch,
SmallVectorImpl<uint32_t> &Insts) {
if (isInt<13>(Addr)) {
// Emit: jmpl %g0+Addr, <scratch>
// nop
Insts.push_back(JMP_INST(0, LO10(Addr), scratch));
Insts.push_back(NOP_INST);
return;
}
if (isUInt<32>(Addr)) {
// Emit: sethi %hi(Addr), scratch
// jmpl scratch+%lo(Addr), scratch
// sub scratch, 4, scratch
Insts.push_back(SETHI_INST(HI22(Addr), scratch));
Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
Insts.push_back(SUB_INST(scratch, 4, scratch));
return;
}
if (Addr < 0 && isInt<33>(Addr)) {
// Emit: sethi %hix(Addr), scratch)
// xor scratch, %lox(Addr), scratch
// jmpl scratch+0, scratch
// sub scratch, 8, scratch
Insts.push_back(SETHI_INST(HIX22(Addr), scratch));
Insts.push_back(XOR_INST(scratch, LOX10(Addr), scratch));
Insts.push_back(JMP_INST(scratch, 0, scratch));
Insts.push_back(SUB_INST(scratch, 8, scratch));
return;
}
// Emit: rd %pc, scratch
// ldx [scratch+16], scratch
// jmpl scratch+0, scratch
// sub scratch, 8, scratch
// <Addr: 8 byte>
Insts.push_back(RDPC_INST(scratch));
Insts.push_back(LDX_INST(scratch, 16, scratch));
Insts.push_back(JMP_INST(scratch, 0, scratch));
Insts.push_back(SUB_INST(scratch, 8, scratch));
Insts.push_back((uint32_t)(((int64_t)Addr) >> 32) & 0xffffffff);
Insts.push_back((uint32_t)(Addr & 0xffffffff));
// Instruction sequence without rdpc instruction
// 7 instruction and 2 scratch register
// Emit: sethi %hh(Addr), scratch
// or scratch, %hm(Addr), scratch
// sllx scratch, 32, scratch
// sethi %hi(Addr), scratch2
// or scratch, scratch2, scratch
// jmpl scratch+%lo(Addr), scratch
// sub scratch, 20, scratch
// Insts.push_back(SETHI_INST(HH22(Addr), scratch));
// Insts.push_back(OR_INST_I(scratch, HM10(Addr), scratch));
// Insts.push_back(SLLX_INST(scratch, 32, scratch));
// Insts.push_back(SETHI_INST(HI22(Addr), scratch2));
// Insts.push_back(OR_INST_R(scratch, scratch2, scratch));
// Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
// Insts.push_back(SUB_INST(scratch, 20, scratch));
}
extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {
// Get the address of the compiled code for this function.
intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
// Rewrite the function stub so that we don't end up here every time we
// execute the call. We're replacing the stub instructions with code
// that jumps to the compiled function:
SmallVector<uint32_t, 8> Insts;
intptr_t diff = (NewVal - StubAddr) >> 2;
if (isInt<22>(diff)) {
// Use branch instruction to jump
Insts.push_back(BA_INST(diff));
Insts.push_back(NOP_INST);
} else {
// Otherwise, use indirect jump to the compiled function
emitInstrForIndirectJump(NewVal, 1, Insts);
}
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
*(uint32_t *)(StubAddr + i*4) = Insts[i];
sys::Memory::InvalidateInstructionCache((void*) StubAddr, Insts.size() * 4);
return (void*)StubAddr;
}
void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
llvm_unreachable("FIXME: Implement SparcJITInfo::"
"replaceMachineCodeForFunction");
}
TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() {
// The stub contains maximum of 4 4-byte instructions and 8 bytes for address,
// aligned at 32 bytes.
// See emitFunctionStub and emitInstrForIndirectJump for details.
StubLayout Result = { 4*4 + 8, 32 };
return Result;
}
void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE)
{
JCE.emitAlignment(32);
void *Addr = (void*) (JCE.getCurrentPCValue());
intptr_t CurrentAddr = (intptr_t)Addr;
intptr_t EmittedAddr;
SmallVector<uint32_t, 8> Insts;
if (Fn != (void*)(intptr_t)SparcCompilationCallback) {
EmittedAddr = (intptr_t)Fn;
intptr_t diff = (EmittedAddr - CurrentAddr) >> 2;
if (isInt<22>(diff)) {
Insts.push_back(BA_INST(diff));
Insts.push_back(NOP_INST);
}
} else {
EmittedAddr = (intptr_t)SparcCompilationCallback;
}
if (Insts.size() == 0)
emitInstrForIndirectJump(EmittedAddr, 1, Insts);
if (!sys::Memory::setRangeWritable(Addr, 4 * Insts.size()))
llvm_unreachable("ERROR: Unable to mark stub writable.");
for (unsigned i = 0, e = Insts.size(); i != e; ++i)
JCE.emitWordBE(Insts[i]);
sys::Memory::InvalidateInstructionCache(Addr, 4 * Insts.size());
if (!sys::Memory::setRangeExecutable(Addr, 4 * Insts.size()))
llvm_unreachable("ERROR: Unable to mark stub executable.");
return Addr;
}
TargetJITInfo::LazyResolverFn
SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) {
JITCompilerFunction = F;
return SparcCompilationCallback;
}
/// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols.
void SparcJITInfo::relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase) {
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
void *RelocPos = (char*) Function + MR->getMachineCodeOffset();
intptr_t ResultPtr = (intptr_t) MR->getResultPointer();
switch ((SP::RelocationType) MR->getRelocationType()) {
case SP::reloc_sparc_hi:
ResultPtr = (ResultPtr >> 10) & 0x3fffff;
break;
case SP::reloc_sparc_lo:
ResultPtr = (ResultPtr & 0x3ff);
break;
case SP::reloc_sparc_pc30:
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffffff;
break;
case SP::reloc_sparc_pc22:
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffff;
break;
case SP::reloc_sparc_pc19:
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff;
break;
case SP::reloc_sparc_h44:
ResultPtr = (ResultPtr >> 22) & 0x3fffff;
break;
case SP::reloc_sparc_m44:
ResultPtr = (ResultPtr >> 12) & 0x3ff;
break;
case SP::reloc_sparc_l44:
ResultPtr = (ResultPtr & 0xfff);
break;
case SP::reloc_sparc_hh:
ResultPtr = (((int64_t)ResultPtr) >> 42) & 0x3fffff;
break;
case SP::reloc_sparc_hm:
ResultPtr = (((int64_t)ResultPtr) >> 32) & 0x3ff;
break;
}
*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
}
}

67
lib/Target/Sparc/SparcJITInfo.h
View File

@@ -1,67 +0,0 @@
//==- SparcJITInfo.h - Sparc Implementation of the JIT Interface -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the declaration of the SparcJITInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef SPARCJITINFO_H
#define SPARCJITINFO_H
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetJITInfo.h"
namespace llvm {
class SparcTargetMachine;
class SparcJITInfo : public TargetJITInfo {
bool IsPIC;
public:
explicit SparcJITInfo()
: IsPIC(false) {}
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
void replaceMachineCodeForFunction(void *Old, void *New) override;
// getStubLayout - Returns the size and alignment of the largest call stub
// on Sparc.
StubLayout getStubLayout() override;
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
/// small native function that simply calls the function at the specified
/// address.
void *emitFunctionStub(const Function *F, void *Fn,
JITCodeEmitter &JCE) override;
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
/// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols.
void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char *GOTBase) override;
/// Initialize - Initialize internal stage for the function being JITted.
void Initialize(const MachineFunction &MF, bool isPIC) {
IsPIC = isPIC;
}
};
}
#endif

3
lib/Target/Sparc/SparcSubtarget.h
View File

@@ -17,7 +17,6 @@
#include "SparcFrameLowering.h"
#include "SparcInstrInfo.h"
#include "SparcISelLowering.h"
#include "SparcJITInfo.h"
#include "SparcSelectionDAGInfo.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetFrameLowering.h"
@@ -43,7 +42,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
SparcTargetLowering TLInfo;
SparcSelectionDAGInfo TSInfo;
SparcFrameLowering FrameLowering;
SparcJITInfo JITInfo;
public:
SparcSubtarget(const std::string &TT, const std::string &CPU,
@@ -62,7 +60,6 @@ public:
const SparcSelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
SparcJITInfo *getJITInfo() override { return &JITInfo; }
const DataLayout *getDataLayout() const override { return &DL; }
bool isV9() const { return IsV9; }

7
lib/Target/Sparc/SparcTargetMachine.cpp
View File

@@ -61,13 +61,6 @@ bool SparcPassConfig::addInstSelector() {
return false;
}
bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
JITCodeEmitter &JCE) {
// Machine code emitter pass for Sparc.
PM.add(createSparcJITCodeEmitterPass(*this, JCE));
return false;
}
/// addPreEmitPass - This pass may be implemented by targets that want to run
/// passes immediately before machine code is emitted. This should return
/// true if -print-machineinstrs should print out the code after the passes.

5
lib/Target/Sparc/SparcTargetMachine.h
View File

@@ -30,13 +30,8 @@ public:
const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; }
SparcSubtarget *getSubtargetImpl() {
return static_cast<SparcSubtarget *>(TargetMachine::getSubtargetImpl());
}
// Pass Pipeline Configuration
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
};
/// SparcV8TargetMachine - Sparc 32-bit target machine