6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-21 03:29:40 +00:00
Code Issues Projects Releases Wiki Activity

Fix the move to/from accumulator register instructions that use a full 64-bit

Browse Source 
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2013-07-22 21:25:31 +00:00
parent dca13e0b3f
commit 877d123bdb
4 changed files with 95 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/X86/X86InstrFormats.td
View File

@ -628,6 +628,13 @@ class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
let CodeSize = 3;
}
class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: X86Inst<o, f, Imm64, outs, ins, asm, itin> {
let Pattern = pattern;
let CodeSize = 3;
}
class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern, InstrItinClass itin = NoItinerary>
: SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;

40
lib/Target/X86/X86InstrInfo.td
View File

@ -1060,21 +1060,33 @@ def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
Requires<[In32BitMode]>;
}
// FIXME: These definitions are utterly broken
// Just leave them commented out for now because they're useless outside
// of the large code model, and most compilers won't generate the instructions
// in question.
/*
def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
"mov{q}\t{$src, %rax|RAX, $src}", []>;
def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
"mov{q}\t{$src, %rax|RAX, $src}", []>;
def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
*/
// These forms all have full 64-bit absolute addresses in their instructions
// and use the movabs mnemonic to indicate this specific form.
def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src),
"movabs{b}\t{$src, %al|AL, $src}", []>,
Requires<[In64BitMode]>;
def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
"movabs{w}\t{$src, %ax|AX, $src}", []>, OpSize,
Requires<[In64BitMode]>;
def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
"movabs{l}\t{$src, %eax|AEX, $src}", []>,
Requires<[In64BitMode]>;
def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
"movabs{q}\t{$src, %rax|RAX, $src}", []>,
Requires<[In64BitMode]>;
def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins),
"movabs{b}\t{%al, $dst|$dst, AL}", []>,
Requires<[In64BitMode]>;
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
"movabs{w}\t{%ax, $dst|$dst, AX}", []>, OpSize,
Requires<[In64BitMode]>;
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
"movabs{l}\t{%eax, $dst|$dst, EAX}", []>,
Requires<[In64BitMode]>;
def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
"movabs{q}\t{%rax, $dst|$dst, RAX}", []>,
Requires<[In64BitMode]>;
let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),

30
test/MC/Disassembler/X86/x86-64.txt
View File

@ -127,3 +127,33 @@
# CHECK: stac
0x0f 0x01 0xcb
# CHECK: movabsb -6066930261531658096, %al
0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb -6066930261531658096, %al
0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw -6066930261531658096, %ax
0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl -6066930261531658096, %eax
0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq -6066930261531658096, %rax
0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsb %al, -6066930261531658096
0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsw %ax, -6066930261531658096
0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsl %eax, -6066930261531658096
0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
# CHECK: movabsq %rax, -6066930261531658096
0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab

32
test/MC/X86/x86-64.s
View File

@ -672,6 +672,38 @@ movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00
// CHECK: encoding: [0x48,0xc7,0xc0,0x0a,0x00,0x00,0x00]
movq $10, %rax
// CHECK: movabsb -6066930261531658096, %al
// CHECK: encoding: [0xa0,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsb 0xabcdef1234567890,%al
// CHECK: movabsw -6066930261531658096, %ax
// CHECK: encoding: [0x66,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsw 0xabcdef1234567890,%ax
// CHECK: movabsl -6066930261531658096, %eax
// CHECK: encoding: [0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsl 0xabcdef1234567890,%eax
// CHECK: movabsq -6066930261531658096, %rax
// CHECK: encoding: [0x48,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsq 0xabcdef1234567890, %rax
// CHECK: movabsb %al, -6066930261531658096
// CHECK: encoding: [0xa2,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsb %al,0xabcdef1234567890
// CHECK: movabsw %ax, -6066930261531658096
// CHECK: encoding: [0x66,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsw %ax,0xabcdef1234567890
// CHECK: movabsl %eax, -6066930261531658096
// CHECK: encoding: [0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsl %eax,0xabcdef1234567890
// CHECK: movabsq %rax, -6066930261531658096
// CHECK: encoding: [0x48,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
movabsq %rax,0xabcdef1234567890
// rdar://8014869
//
// CHECK: ret