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Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -628,6 +628,13 @@ class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
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let CodeSize = 3;
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}
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class RIi64_NOREX<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm64, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
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@ -1060,21 +1060,33 @@ def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins),
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Requires<[In32BitMode]>;
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}
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// FIXME: These definitions are utterly broken
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// Just leave them commented out for now because they're useless outside
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// of the large code model, and most compilers won't generate the instructions
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// in question.
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/*
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def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src),
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"mov{q}\t{$src, %rax|RAX, $src}", []>;
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def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src),
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"mov{q}\t{$src, %rax|RAX, $src}", []>;
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def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
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def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"mov{q}\t{%rax, $dst|$dst, RAX}", []>;
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*/
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// These forms all have full 64-bit absolute addresses in their instructions
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// and use the movabs mnemonic to indicate this specific form.
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def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src),
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"movabs{b}\t{$src, %al|AL, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{w}\t{$src, %ax|AX, $src}", []>, OpSize,
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Requires<[In64BitMode]>;
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def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{l}\t{$src, %eax|AEX, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src),
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"movabs{q}\t{$src, %rax|RAX, $src}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins),
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"movabs{b}\t{%al, $dst|$dst, AL}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{w}\t{%ax, $dst|$dst, AX}", []>, OpSize,
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Requires<[In64BitMode]>;
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def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{l}\t{%eax, $dst|$dst, EAX}", []>,
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Requires<[In64BitMode]>;
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def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins),
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"movabs{q}\t{%rax, $dst|$dst, RAX}", []>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
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def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
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@ -127,3 +127,33 @@
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# CHECK: stac
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0x0f 0x01 0xcb
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# CHECK: movabsb -6066930261531658096, %al
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0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsb -6066930261531658096, %al
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0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsw -6066930261531658096, %ax
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0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsl -6066930261531658096, %eax
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0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsq -6066930261531658096, %rax
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0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsb %al, -6066930261531658096
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0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsb %al, -6066930261531658096
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0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsw %ax, -6066930261531658096
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0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsl %eax, -6066930261531658096
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0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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# CHECK: movabsq %rax, -6066930261531658096
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0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab
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@ -672,6 +672,38 @@ movl 0, %eax // CHECK: movl 0, %eax # encoding: [0x8b,0x04,0x25,0x00,0x00,0x00
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// CHECK: encoding: [0x48,0xc7,0xc0,0x0a,0x00,0x00,0x00]
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movq $10, %rax
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// CHECK: movabsb -6066930261531658096, %al
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// CHECK: encoding: [0xa0,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsb 0xabcdef1234567890,%al
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// CHECK: movabsw -6066930261531658096, %ax
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// CHECK: encoding: [0x66,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsw 0xabcdef1234567890,%ax
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// CHECK: movabsl -6066930261531658096, %eax
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// CHECK: encoding: [0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsl 0xabcdef1234567890,%eax
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// CHECK: movabsq -6066930261531658096, %rax
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// CHECK: encoding: [0x48,0xa1,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsq 0xabcdef1234567890, %rax
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// CHECK: movabsb %al, -6066930261531658096
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// CHECK: encoding: [0xa2,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsb %al,0xabcdef1234567890
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// CHECK: movabsw %ax, -6066930261531658096
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// CHECK: encoding: [0x66,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsw %ax,0xabcdef1234567890
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// CHECK: movabsl %eax, -6066930261531658096
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// CHECK: encoding: [0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsl %eax,0xabcdef1234567890
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// CHECK: movabsq %rax, -6066930261531658096
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// CHECK: encoding: [0x48,0xa3,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab]
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movabsq %rax,0xabcdef1234567890
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// rdar://8014869
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//
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// CHECK: ret
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