mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 03:29:40 +00:00
Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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@ -166,6 +166,12 @@ namespace llvm {
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return *this;
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}
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}
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/// getScalarType - If this is a vector type, return the element type,
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/// otherwise return this.
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MVT getScalarType() const {
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return isVector() ? getVectorElementType() : *this;
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}
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MVT getVectorElementType() const {
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switch (SimpleTy) {
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@ -524,6 +530,12 @@ namespace llvm {
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return V;
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}
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/// getScalarType - If this is a vector type, return the element type,
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/// otherwise return this.
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EVT getScalarType() const {
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return isVector() ? getVectorElementType() : *this;
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}
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/// getVectorElementType - Given a vector type, return the type of
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/// each element.
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EVT getVectorElementType() const {
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@ -119,7 +119,8 @@ namespace {
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/// it can be simplified or if things it uses can be simplified by bit
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/// propagation. If so, return true.
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bool SimplifyDemandedBits(SDValue Op) {
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APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
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unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
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APInt Demanded = APInt::getAllOnesValue(BitWidth);
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return SimplifyDemandedBits(Op, Demanded);
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}
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@ -2441,7 +2442,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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EVT VT = N0.getValueType();
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unsigned OpSizeInBits = VT.getSizeInBits();
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unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
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// fold (shl c1, c2) -> c1<<c2
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if (N0C && N1C)
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@ -2457,7 +2458,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {
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return N0;
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// if (shl x, c) is known to be zero, return 0
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if (DAG.MaskedValueIsZero(SDValue(N, 0),
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APInt::getAllOnesValue(VT.getSizeInBits())))
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APInt::getAllOnesValue(OpSizeInBits)))
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return DAG.getConstant(0, VT);
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// fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
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if (N1.getOpcode() == ISD::TRUNCATE &&
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@ -2533,6 +2534,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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EVT VT = N0.getValueType();
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unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
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// fold (sra c1, c2) -> (sra c1, c2)
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if (N0C && N1C)
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@ -2544,7 +2546,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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if (N0C && N0C->isAllOnesValue())
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return N0;
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// fold (sra x, (setge c, size(x))) -> undef
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if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
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if (N1C && N1C->getZExtValue() >= OpSizeInBits)
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return DAG.getUNDEF(VT);
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// fold (sra x, 0) -> x
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if (N1C && N1C->isNullValue())
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@ -2552,7 +2554,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
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// sext_inreg.
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if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
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unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
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unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
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EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
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if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
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@ -2563,7 +2565,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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if (N1C && N0.getOpcode() == ISD::SRA) {
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if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
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if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
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if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
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return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
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DAG.getConstant(Sum, N1C->getValueType(0)));
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}
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@ -2579,9 +2581,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
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if (N01C && N1C) {
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// Determine what the truncate's result bitsize and type would be.
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unsigned VTValSize = VT.getSizeInBits();
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EVT TruncVT =
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EVT::getIntegerVT(*DAG.getContext(), VTValSize - N1C->getZExtValue());
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EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
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// Determine the residual right-shift amount.
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signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
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@ -2614,7 +2615,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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EVT TruncVT = N1.getValueType();
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SDValue N100 = N1.getOperand(0).getOperand(0);
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APInt TruncC = N101C->getAPIntValue();
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TruncC.trunc(TruncVT.getSizeInBits());
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TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
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return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
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DAG.getNode(ISD::AND, N->getDebugLoc(),
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TruncVT,
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@ -2643,7 +2644,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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EVT VT = N0.getValueType();
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unsigned OpSizeInBits = VT.getSizeInBits();
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unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
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// fold (srl c1, c2) -> c1 >>u c2
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if (N0C && N1C)
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@ -3036,7 +3037,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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else if (Op.getValueType().bitsGT(VT))
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Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
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DAG.getValueType(N0.getValueType()));
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DAG.getValueType(N0.getValueType().getScalarType()));
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}
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}
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@ -3177,7 +3178,8 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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} else if (Op.getValueType().bitsGT(VT)) {
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Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
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}
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return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
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return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
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N0.getValueType().getScalarType());
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}
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// Fold (zext (and (trunc x), cst)) -> (and x, cst),
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@ -3536,7 +3538,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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SDValue N1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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EVT EVT = cast<VTSDNode>(N1)->getVT();
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unsigned VTBits = VT.getSizeInBits();
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unsigned VTBits = VT.getScalarType().getSizeInBits();
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unsigned EVTBits = EVT.getSizeInBits();
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// fold (sext_in_reg c1) -> c1
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@ -3544,7 +3546,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
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// If the input is already sign extended, just drop the extension.
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if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
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if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
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return N0;
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// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
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@ -3559,7 +3561,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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// if x is small enough.
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if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
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SDValue N00 = N0.getOperand(0);
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if (N00.getValueType().getSizeInBits() < EVTBits)
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if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits)
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return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
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}
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@ -3583,11 +3585,11 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
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if (N0.getOpcode() == ISD::SRL) {
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
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if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
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if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
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// We can turn this into an SRA iff the input to the SRL is already sign
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// extended enough.
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unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
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if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
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if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
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return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
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N0.getOperand(0), N0.getOperand(1));
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}
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@ -2294,9 +2294,16 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
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// NOTE: we could fall back on load/store here too for targets without
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// SAR. However, it is doubtful that any exist.
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EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
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unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
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EVT VT = Node->getValueType(0);
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EVT ShiftAmountTy = TLI.getShiftAmountTy();
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if (ExtraVT.isVector()) ExtraVT = ExtraVT.getVectorElementType();
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if (VT.isVector()) {
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ShiftAmountTy = VT;
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VT = VT.getVectorElementType();
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}
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unsigned BitsDiff = VT.getSizeInBits() -
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ExtraVT.getSizeInBits();
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SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
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SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
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Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
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Node->getOperand(0), ShiftCst);
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Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
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@ -517,6 +517,7 @@ private:
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SDValue ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N);
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SDValue ScalarizeVecRes_LOAD(LoadSDNode *N);
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SDValue ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N);
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SDValue ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode *N);
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SDValue ScalarizeVecRes_SELECT(SDNode *N);
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SDValue ScalarizeVecRes_SELECT_CC(SDNode *N);
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SDValue ScalarizeVecRes_SETCC(SDNode *N);
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@ -560,6 +561,7 @@ private:
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
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@ -602,6 +604,7 @@ private:
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SDValue WidenVecRes_INSERT_VECTOR_ELT(SDNode* N);
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SDValue WidenVecRes_LOAD(SDNode* N);
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SDValue WidenVecRes_SCALAR_TO_VECTOR(SDNode* N);
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SDValue WidenVecRes_SIGN_EXTEND_INREG(SDNode* N);
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SDValue WidenVecRes_SELECT(SDNode* N);
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SDValue WidenVecRes_SELECT_CC(SDNode* N);
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SDValue WidenVecRes_UNDEF(SDNode *N);
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@ -179,6 +179,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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case ISD::FRINT:
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case ISD::FNEARBYINT:
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case ISD::FFLOOR:
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case ISD::SIGN_EXTEND_INREG:
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QueryType = Node->getValueType(0);
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break;
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case ISD::SINT_TO_FP:
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@ -54,6 +54,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
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case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
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case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_SIGN_EXTEND_INREG(N); break;
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case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
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case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
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case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
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@ -195,6 +196,13 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
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return InOp;
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SIGN_EXTEND_INREG(SDNode *N) {
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EVT EltVT = N->getValueType(0).getVectorElementType();
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), EltVT,
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LHS, N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(1));
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return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
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@ -401,6 +409,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
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case ISD::SIGN_EXTEND_INREG: SplitVecRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
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case ISD::LOAD:
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SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
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break;
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@ -700,6 +709,18 @@ void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
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Hi = DAG.getUNDEF(HiVT);
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}
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void DAGTypeLegalizer::SplitVecRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue LHSLo, LHSHi;
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GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
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DebugLoc dl = N->getDebugLoc();
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Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
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N->getOperand(1));
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Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
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N->getOperand(1));
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}
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void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
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SDValue &Hi) {
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assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
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@ -1141,6 +1162,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
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case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
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case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
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case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_SIGN_EXTEND_INREG(N); break;
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case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
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case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
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case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
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@ -1691,6 +1713,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
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WidenVT, N->getOperand(0));
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}
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SDValue DAGTypeLegalizer::WidenVecRes_SIGN_EXTEND_INREG(SDNode *N) {
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EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
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WidenVT, WidenLHS, N->getOperand(1));
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}
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SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
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EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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unsigned WidenNumElts = WidenVT.getVectorNumElements();
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@ -832,8 +832,12 @@ SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT) {
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}
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SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) {
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assert(!VT.isVector() &&
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"getZeroExtendInReg should use the vector element type instead of "
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"the vector type!");
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if (Op.getValueType() == VT) return Op;
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APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
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unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
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APInt Imm = APInt::getLowBitsSet(BitWidth,
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VT.getSizeInBits());
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return getNode(ISD::AND, DL, Op.getValueType(), Op,
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getConstant(Imm, Op.getValueType()));
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@ -1481,7 +1485,7 @@ bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
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if (Op.getValueType().isVector())
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return false;
|
||||
|
||||
unsigned BitWidth = Op.getValueSizeInBits();
|
||||
unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
|
||||
return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
|
||||
}
|
||||
|
||||
@ -1504,7 +1508,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
APInt &KnownZero, APInt &KnownOne,
|
||||
unsigned Depth) const {
|
||||
unsigned BitWidth = Mask.getBitWidth();
|
||||
assert(BitWidth == Op.getValueType().getSizeInBits() &&
|
||||
assert(BitWidth == Op.getValueType().getScalarType().getSizeInBits() &&
|
||||
"Mask size mismatches value type size!");
|
||||
|
||||
KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
|
||||
@ -1761,7 +1765,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
}
|
||||
case ISD::ZERO_EXTEND: {
|
||||
EVT InVT = Op.getOperand(0).getValueType();
|
||||
unsigned InBits = InVT.getSizeInBits();
|
||||
unsigned InBits = InVT.getScalarType().getSizeInBits();
|
||||
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
|
||||
APInt InMask = Mask;
|
||||
InMask.trunc(InBits);
|
||||
@ -1775,7 +1779,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
}
|
||||
case ISD::SIGN_EXTEND: {
|
||||
EVT InVT = Op.getOperand(0).getValueType();
|
||||
unsigned InBits = InVT.getSizeInBits();
|
||||
unsigned InBits = InVT.getScalarType().getSizeInBits();
|
||||
APInt InSignBit = APInt::getSignBit(InBits);
|
||||
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
|
||||
APInt InMask = Mask;
|
||||
@ -1816,7 +1820,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
}
|
||||
case ISD::ANY_EXTEND: {
|
||||
EVT InVT = Op.getOperand(0).getValueType();
|
||||
unsigned InBits = InVT.getSizeInBits();
|
||||
unsigned InBits = InVT.getScalarType().getSizeInBits();
|
||||
APInt InMask = Mask;
|
||||
InMask.trunc(InBits);
|
||||
KnownZero.trunc(InBits);
|
||||
@ -1828,7 +1832,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
}
|
||||
case ISD::TRUNCATE: {
|
||||
EVT InVT = Op.getOperand(0).getValueType();
|
||||
unsigned InBits = InVT.getSizeInBits();
|
||||
unsigned InBits = InVT.getScalarType().getSizeInBits();
|
||||
APInt InMask = Mask;
|
||||
InMask.zext(InBits);
|
||||
KnownZero.zext(InBits);
|
||||
@ -1961,7 +1965,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
|
||||
unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
|
||||
EVT VT = Op.getValueType();
|
||||
assert(VT.isInteger() && "Invalid VT!");
|
||||
unsigned VTBits = VT.getSizeInBits();
|
||||
unsigned VTBits = VT.getScalarType().getSizeInBits();
|
||||
unsigned Tmp, Tmp2;
|
||||
unsigned FirstAnswer = 1;
|
||||
|
||||
@ -1988,7 +1992,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
|
||||
}
|
||||
|
||||
case ISD::SIGN_EXTEND:
|
||||
Tmp = VTBits-Op.getOperand(0).getValueType().getSizeInBits();
|
||||
Tmp = VTBits-Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
|
||||
return ComputeNumSignBits(Op.getOperand(0), Depth+1) + Tmp;
|
||||
|
||||
case ISD::SIGN_EXTEND_INREG:
|
||||
@ -2624,6 +2628,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
|
||||
assert(VT == N1.getValueType() && "Not an inreg extend!");
|
||||
assert(VT.isInteger() && EVT.isInteger() &&
|
||||
"Cannot *_EXTEND_INREG FP types");
|
||||
assert(!EVT.isVector() &&
|
||||
"AssertSExt/AssertZExt type should be the vector element type "
|
||||
"rather than the vector type!");
|
||||
assert(EVT.bitsLE(VT) && "Not extending!");
|
||||
if (VT == EVT) return N1; // noop assertion.
|
||||
break;
|
||||
@ -2633,12 +2640,15 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
|
||||
assert(VT == N1.getValueType() && "Not an inreg extend!");
|
||||
assert(VT.isInteger() && EVT.isInteger() &&
|
||||
"Cannot *_EXTEND_INREG FP types");
|
||||
assert(EVT.bitsLE(VT) && "Not extending!");
|
||||
assert(!EVT.isVector() &&
|
||||
"SIGN_EXTEND_INREG type should be the vector element type rather "
|
||||
"than the vector type!");
|
||||
assert(EVT.bitsLE(VT.getScalarType()) && "Not extending!");
|
||||
if (EVT == VT) return N1; // Not actually extending
|
||||
|
||||
if (N1C) {
|
||||
APInt Val = N1C->getAPIntValue();
|
||||
unsigned FromBits = cast<VTSDNode>(N2)->getVT().getSizeInBits();
|
||||
unsigned FromBits = EVT.getSizeInBits();
|
||||
Val <<= Val.getBitWidth()-FromBits;
|
||||
Val = Val.ashr(Val.getBitWidth()-FromBits);
|
||||
return getConstant(Val, VT);
|
||||
|
@ -911,7 +911,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
|
||||
TargetLoweringOpt &TLO,
|
||||
unsigned Depth) const {
|
||||
unsigned BitWidth = DemandedMask.getBitWidth();
|
||||
assert(Op.getValueSizeInBits() == BitWidth &&
|
||||
assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
|
||||
"Mask size mismatches value type size!");
|
||||
APInt NewMask = DemandedMask;
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
@ -1240,7 +1240,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
|
||||
// demand the input sign bit.
|
||||
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
|
||||
if (HighBits.intersects(NewMask))
|
||||
InDemandedMask |= APInt::getSignBit(VT.getSizeInBits());
|
||||
InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
|
||||
|
||||
if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
|
||||
KnownZero, KnownOne, TLO, Depth+1))
|
||||
|
@ -595,6 +595,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
|
||||
setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
|
||||
setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
|
||||
setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
|
||||
setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
|
||||
}
|
||||
|
||||
// FIXME: In order to prevent SSE instructions being expanded to MMX ones
|
||||
|
37
test/CodeGen/X86/vec_ext_inreg.ll
Normal file
37
test/CodeGen/X86/vec_ext_inreg.ll
Normal file
@ -0,0 +1,37 @@
|
||||
; RUN: llc < %s -march=x86-64
|
||||
|
||||
define <8 x i32> @a(<8 x i32> %a) nounwind {
|
||||
%b = trunc <8 x i32> %a to <8 x i16>
|
||||
%c = sext <8 x i16> %b to <8 x i32>
|
||||
ret <8 x i32> %c
|
||||
}
|
||||
|
||||
define <3 x i32> @b(<3 x i32> %a) nounwind {
|
||||
%b = trunc <3 x i32> %a to <3 x i16>
|
||||
%c = sext <3 x i16> %b to <3 x i32>
|
||||
ret <3 x i32> %c
|
||||
}
|
||||
|
||||
define <1 x i32> @c(<1 x i32> %a) nounwind {
|
||||
%b = trunc <1 x i32> %a to <1 x i16>
|
||||
%c = sext <1 x i16> %b to <1 x i32>
|
||||
ret <1 x i32> %c
|
||||
}
|
||||
|
||||
define <8 x i32> @d(<8 x i32> %a) nounwind {
|
||||
%b = trunc <8 x i32> %a to <8 x i16>
|
||||
%c = zext <8 x i16> %b to <8 x i32>
|
||||
ret <8 x i32> %c
|
||||
}
|
||||
|
||||
define <3 x i32> @e(<3 x i32> %a) nounwind {
|
||||
%b = trunc <3 x i32> %a to <3 x i16>
|
||||
%c = zext <3 x i16> %b to <3 x i32>
|
||||
ret <3 x i32> %c
|
||||
}
|
||||
|
||||
define <1 x i32> @f(<1 x i32> %a) nounwind {
|
||||
%b = trunc <1 x i32> %a to <1 x i16>
|
||||
%c = zext <1 x i16> %b to <1 x i32>
|
||||
ret <1 x i32> %c
|
||||
}
|
Loading…
Reference in New Issue
Block a user