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Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-09-11 01:01:31 +00:00
parent 5f12c21320
commit 879caeadf3
2 changed files with 17 additions and 1 deletions
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16
lib/Target/X86/X86InstrInfo.cpp
View File

@ -2206,6 +2206,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
unsigned MinAlign = I->second.second; unsigned MinAlign = I->second.second;
if (Align < MinAlign) if (Align < MinAlign)
return NULL; return NULL;
bool NarrowToMOV32rm = false;
if (Size) { if (Size) {
unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
if (Size < RCSize) { if (Size < RCSize) {
@ -2216,7 +2217,10 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
// If this is a 64-bit load, but the spill slot is 32, then we can do // If this is a 64-bit load, but the spill slot is 32, then we can do
// a 32-bit load which is implicitly zero-extended. This likely is due // a 32-bit load which is implicitly zero-extended. This likely is due
// to liveintervalanalysis remat'ing a load from stack slot. // to liveintervalanalysis remat'ing a load from stack slot.
if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
return NULL;
Opcode = X86::MOV32rm; Opcode = X86::MOV32rm;
NarrowToMOV32rm = true;
} }
} }
@ -2224,6 +2228,18 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
else else
NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
if (NarrowToMOV32rm) {
// If this is the special case where we use a MOV32rm to load a 32-bit
// value and zero-extend the top bits. Change the destination register
// to a 32-bit one.
unsigned DstReg = NewMI->getOperand(0).getReg();
if (TargetRegisterInfo::isPhysicalRegister(DstReg))
NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
4/*x86_subreg_32bit*/));
else
NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
}
return NewMI; return NewMI;
} }
} }

2
test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll
View File

@ -13,7 +13,7 @@ define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64
entry: entry:
; CHECK: _t: ; CHECK: _t:
; CHECK: movl 16(%rbp), ; CHECK: movl 16(%rbp),
; CHECK: movl 16(%rbp), ; CHECK: movl 16(%rbp), %edx
%0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1] %0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1]
%1 = zext i32 %clientPort to i64 ; <i64> [#uses=1] %1 = zext i32 %clientPort to i64 ; <i64> [#uses=1]
%2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1] %2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1]