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Follow up to 81494. When the folded reload is narrowed to a 32-bit load then change the destination register to a 32-bit one or add a sub-register index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81496 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2206,6 +2206,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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unsigned MinAlign = I->second.second;
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if (Align < MinAlign)
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return NULL;
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bool NarrowToMOV32rm = false;
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if (Size) {
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unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
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if (Size < RCSize) {
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@ -2216,7 +2217,10 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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// If this is a 64-bit load, but the spill slot is 32, then we can do
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// a 32-bit load which is implicitly zero-extended. This likely is due
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// to liveintervalanalysis remat'ing a load from stack slot.
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if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
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return NULL;
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Opcode = X86::MOV32rm;
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NarrowToMOV32rm = true;
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}
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}
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@ -2224,6 +2228,18 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
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NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
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else
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NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
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if (NarrowToMOV32rm) {
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// If this is the special case where we use a MOV32rm to load a 32-bit
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// value and zero-extend the top bits. Change the destination register
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// to a 32-bit one.
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unsigned DstReg = NewMI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg))
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NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
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4/*x86_subreg_32bit*/));
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else
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NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
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}
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return NewMI;
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}
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}
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@ -13,7 +13,7 @@ define i32 @t(i32 %clientPort, i32 %pluginID, i32 %requestID, i32 %objectID, i64
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entry:
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; CHECK: _t:
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; CHECK: movl 16(%rbp),
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; CHECK: movl 16(%rbp),
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; CHECK: movl 16(%rbp), %edx
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%0 = zext i32 %argumentsLength to i64 ; <i64> [#uses=1]
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%1 = zext i32 %clientPort to i64 ; <i64> [#uses=1]
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%2 = inttoptr i64 %1 to %struct.ComplexType* ; <%struct.ComplexType*> [#uses=1]
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