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Fix the alignment of loads from constant pool entries when the

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load address has an offset from the base of the constant pool
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-09-22 22:40:08 +00:00
parent 2165e1288e
commit 87a0f10dc7
2 changed files with 7 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -5438,6 +5438,7 @@ ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
@ -5589,6 +5590,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
if (DestVT == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,

6
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -2042,12 +2042,16 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
if (TLI.isBigEndian()) std::swap(Zero, Four);
SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
Zero, Four);
unsigned Alignment =
1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
Alignment = std::min(Alignment, 4u);
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
FudgePtr, NULL, 0, MVT::f32);
FudgePtr, NULL, 0, MVT::f32,
false, Alignment);
return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
}