mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
remove some unused instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24794 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
2cfdbb2716
commit
87a63f812c
@ -242,12 +242,6 @@ def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst", []>;
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def ANDCCri : F3_2<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andcc $b, $c, $dst", []>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst",
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@ -255,12 +249,6 @@ def ANDNrr : F3_1<2, 0b000101,
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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def ANDNCCrr: F3_1<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andncc $b, $c, $dst", []>;
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def ANDNCCri: F3_2<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andncc $b, $c, $dst", []>;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"or $b, $c, $dst",
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@ -269,12 +257,6 @@ def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst", []>;
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def ORCCri : F3_2<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orcc $b, $c, $dst", []>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst",
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@ -282,12 +264,6 @@ def ORNrr : F3_1<2, 0b000110,
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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def ORNCCrr : F3_1<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orncc $b, $c, $dst", []>;
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def ORNCCri : F3_2<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orncc $b, $c, $dst", []>;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xor $b, $c, $dst",
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@ -296,12 +272,6 @@ def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst", []>;
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def XORCCri : F3_2<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xorcc $b, $c, $dst", []>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst",
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@ -309,12 +279,6 @@ def XNORrr : F3_1<2, 0b000111,
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst", []>;
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def XNORCCrr: F3_1<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnorcc $b, $c, $dst", []>;
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def XNORCCri: F3_2<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnorcc $b, $c, $dst", []>;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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@ -363,12 +327,6 @@ def ADDXrr : F3_1<2, 0b001000,
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addx $b, $c, $dst", []>;
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def ADDXCCrr: F3_1<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addxcc $b, $c, $dst", []>;
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def ADDXCCri: F3_2<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addxcc $b, $c, $dst", []>;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100,
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@ -379,24 +337,21 @@ def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst", []>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst", []>;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subx $b, $c, $dst", []>;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subx $b, $c, $dst", []>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst", []>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst", []>;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst", []>;
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def SUBXCCri: F3_2<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subxcc $b, $c, $dst", []>;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010,
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@ -411,18 +366,6 @@ def SMULrr : F3_1<2, 0b001011,
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def SMULri : F3_2<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smul $b, $c, $dst", []>;
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def UMULCCrr: F3_1<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umulcc $b, $c, $dst", []>;
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def UMULCCri: F3_2<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umulcc $b, $c, $dst", []>;
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def SMULCCrr: F3_1<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smulcc $b, $c, $dst", []>;
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def SMULCCri: F3_2<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smulcc $b, $c, $dst", []>;
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr : F3_1<2, 0b001110,
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@ -437,18 +380,6 @@ def SDIVrr : F3_1<2, 0b001111,
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def SDIVri : F3_2<2, 0b001111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sdiv $b, $c, $dst", []>;
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def UDIVCCrr : F3_1<2, 0b011110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"udivcc $b, $c, $dst", []>;
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def UDIVCCri : F3_2<2, 0b011110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"udivcc $b, $c, $dst", []>;
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def SDIVCCrr : F3_1<2, 0b011111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sdivcc $b, $c, $dst", []>;
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def SDIVCCri : F3_2<2, 0b011111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sdivcc $b, $c, $dst", []>;
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100,
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@ -625,12 +556,6 @@ def FCMPS : F3_3<2, 0b110101, 0b001010001,
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def FCMPD : F3_3<2, 0b110101, 0b001010010,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmpd $src1, $src2\n\tnop">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101,
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(ops FPRegs:$src1, FPRegs:$src2),
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"fcmpes $src1, $src2\n\tnop">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110,
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(ops DFPRegs:$src1, DFPRegs:$src2),
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"fcmped $src1, $src2\n\tnop">;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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@ -242,12 +242,6 @@ def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst", []>;
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def ANDCCri : F3_2<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andcc $b, $c, $dst", []>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst",
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@ -255,12 +249,6 @@ def ANDNrr : F3_1<2, 0b000101,
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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def ANDNCCrr: F3_1<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andncc $b, $c, $dst", []>;
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def ANDNCCri: F3_2<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andncc $b, $c, $dst", []>;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"or $b, $c, $dst",
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@ -269,12 +257,6 @@ def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst", []>;
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def ORCCri : F3_2<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orcc $b, $c, $dst", []>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst",
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@ -282,12 +264,6 @@ def ORNrr : F3_1<2, 0b000110,
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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def ORNCCrr : F3_1<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orncc $b, $c, $dst", []>;
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def ORNCCri : F3_2<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orncc $b, $c, $dst", []>;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xor $b, $c, $dst",
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@ -296,12 +272,6 @@ def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst", []>;
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def XORCCri : F3_2<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xorcc $b, $c, $dst", []>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst",
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@ -309,12 +279,6 @@ def XNORrr : F3_1<2, 0b000111,
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst", []>;
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def XNORCCrr: F3_1<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnorcc $b, $c, $dst", []>;
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def XNORCCri: F3_2<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnorcc $b, $c, $dst", []>;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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@ -363,12 +327,6 @@ def ADDXrr : F3_1<2, 0b001000,
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addx $b, $c, $dst", []>;
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def ADDXCCrr: F3_1<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addxcc $b, $c, $dst", []>;
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def ADDXCCri: F3_2<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addxcc $b, $c, $dst", []>;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100,
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@ -379,24 +337,21 @@ def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst", []>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst", []>;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subx $b, $c, $dst", []>;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subx $b, $c, $dst", []>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst", []>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst", []>;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst", []>;
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def SUBXCCri: F3_2<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subxcc $b, $c, $dst", []>;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010,
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@ -411,18 +366,6 @@ def SMULrr : F3_1<2, 0b001011,
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def SMULri : F3_2<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smul $b, $c, $dst", []>;
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def UMULCCrr: F3_1<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umulcc $b, $c, $dst", []>;
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def UMULCCri: F3_2<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umulcc $b, $c, $dst", []>;
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def SMULCCrr: F3_1<2, 0b011011,
|
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"smulcc $b, $c, $dst", []>;
|
||||
def SMULCCri: F3_2<2, 0b011011,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"smulcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.19 - Divide Instructions, p. 115
|
||||
def UDIVrr : F3_1<2, 0b001110,
|
||||
@ -437,18 +380,6 @@ def SDIVrr : F3_1<2, 0b001111,
|
||||
def SDIVri : F3_2<2, 0b001111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdiv $b, $c, $dst", []>;
|
||||
def UDIVCCrr : F3_1<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"udivcc $b, $c, $dst", []>;
|
||||
def UDIVCCri : F3_2<2, 0b011110,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"udivcc $b, $c, $dst", []>;
|
||||
def SDIVCCrr : F3_1<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"sdivcc $b, $c, $dst", []>;
|
||||
def SDIVCCri : F3_2<2, 0b011111,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"sdivcc $b, $c, $dst", []>;
|
||||
|
||||
// Section B.20 - SAVE and RESTORE, p. 117
|
||||
def SAVErr : F3_1<2, 0b111100,
|
||||
@ -625,12 +556,6 @@ def FCMPS : F3_3<2, 0b110101, 0b001010001,
|
||||
def FCMPD : F3_3<2, 0b110101, 0b001010010,
|
||||
(ops DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fcmpd $src1, $src2\n\tnop">;
|
||||
def FCMPES : F3_3<2, 0b110101, 0b001010101,
|
||||
(ops FPRegs:$src1, FPRegs:$src2),
|
||||
"fcmpes $src1, $src2\n\tnop">;
|
||||
def FCMPED : F3_3<2, 0b110101, 0b001010110,
|
||||
(ops DFPRegs:$src1, DFPRegs:$src2),
|
||||
"fcmped $src1, $src2\n\tnop">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
|
||||
Loading…
Reference in New Issue
Block a user