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ARM sched model: Add branch instructions
Reapply 183263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183428 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
3ba4778c95
commit
87aab6dc96
@ -1941,14 +1941,14 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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// ARMV4T and above
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def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
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"bx", "\tlr", [(ARMretflag)]>,
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Requires<[IsARM, HasV4T]> {
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Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
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let Inst{27-0} = 0b0001001011111111111100011110;
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}
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// ARMV4 only
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def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
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"mov", "\tpc, lr", [(ARMretflag)]>,
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Requires<[IsARM, NoV4T]> {
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Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
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let Inst{27-0} = 0b0001101000001111000000001110;
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}
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}
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@ -1958,7 +1958,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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// ARMV4T and above
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def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
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[(brind GPR:$dst)]>,
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Requires<[IsARM, HasV4T]> {
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Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
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bits<4> dst;
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let Inst{31-4} = 0b1110000100101111111111110001;
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let Inst{3-0} = dst;
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@ -1966,7 +1966,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
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"bx", "\t$dst", [/* pattern left blank */]>,
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Requires<[IsARM, HasV4T]> {
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Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
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bits<4> dst;
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let Inst{27-4} = 0b000100101111111111110001;
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let Inst{3-0} = dst;
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@ -1983,7 +1983,7 @@ let isCall = 1,
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def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
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IIC_Br, "bl\t$func",
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[(ARMcall tglobaladdr:$func)]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>, Sched<[WriteBrL]> {
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let Inst{31-28} = 0b1110;
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bits<24> func;
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let Inst{23-0} = func;
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@ -1993,7 +1993,7 @@ let isCall = 1,
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def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
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IIC_Br, "bl", "\t$func",
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[(ARMcall_pred tglobaladdr:$func)]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>, Sched<[WriteBrL]> {
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bits<24> func;
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let Inst{23-0} = func;
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let DecoderMethod = "DecodeBranchImmInstruction";
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@ -2003,7 +2003,7 @@ let isCall = 1,
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def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
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IIC_Br, "blx\t$func",
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[(ARMcall GPR:$func)]>,
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Requires<[IsARM, HasV5T]> {
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Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
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bits<4> func;
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let Inst{31-4} = 0b1110000100101111111111110011;
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let Inst{3-0} = func;
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@ -2012,7 +2012,7 @@ let isCall = 1,
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def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
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IIC_Br, "blx", "\t$func",
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[(ARMcall_pred GPR:$func)]>,
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Requires<[IsARM, HasV5T]> {
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Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
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bits<4> func;
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let Inst{27-4} = 0b000100101111111111110011;
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let Inst{3-0} = func;
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@ -2022,18 +2022,18 @@ let isCall = 1,
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// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
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def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
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8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, HasV4T]>;
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Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
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// ARMv4
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def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
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8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, NoV4T]>;
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Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
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// mov lr, pc; b if callee is marked noreturn to avoid confusing the
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// return stack predictor.
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def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
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8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
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Requires<[IsARM]>;
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Requires<[IsARM]>, Sched<[WriteBr]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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@ -2041,7 +2041,8 @@ let isBranch = 1, isTerminator = 1 in {
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// a two-value operand where a dag node expects two operands. :(
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def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
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IIC_Br, "b", "\t$target",
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[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
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[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
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Sched<[WriteBr]> {
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bits<24> target;
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let Inst{23-0} = target;
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let DecoderMethod = "DecodeBranchImmInstruction";
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@ -2054,25 +2055,27 @@ let isBranch = 1, isTerminator = 1 in {
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// should be sufficient.
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// FIXME: Is B really a Barrier? That doesn't seem right.
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def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
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[(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
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[(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
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Sched<[WriteBr]>;
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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def BR_JTr : ARMPseudoInst<(outs),
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(ins GPR:$target, i32imm:$jt, i32imm:$id),
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0, IIC_Br,
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
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Sched<[WriteBr]>;
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// FIXME: This shouldn't use the generic "addrmode2," but rather be split
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// into i12 and rs suffixed versions.
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def BR_JTm : ARMPseudoInst<(outs),
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(ins addrmode2:$target, i32imm:$jt, i32imm:$id),
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0, IIC_Br,
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]>;
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imm:$id)]>, Sched<[WriteBrTbl]>;
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def BR_JTadd : ARMPseudoInst<(outs),
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(ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
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0, IIC_Br,
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[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
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imm:$id)]>;
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imm:$id)]>, Sched<[WriteBrTbl]>;
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} // isNotDuplicable = 1, isIndirectBranch = 1
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} // isBarrier = 1
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@ -2081,7 +2084,7 @@ let isBranch = 1, isTerminator = 1 in {
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// BLX (immediate)
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def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
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"blx\t$target", []>,
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Requires<[IsARM, HasV5T]> {
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Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
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let Inst{31-25} = 0b1111101;
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bits<25> target;
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let Inst{23-0} = target{24-1};
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@ -2090,7 +2093,7 @@ def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
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// Branch and Exchange Jazelle
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def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
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[/* pattern left blank */]> {
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[/* pattern left blank */]>, Sched<[WriteBr]> {
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bits<4> func;
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let Inst{23-20} = 0b0010;
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let Inst{19-8} = 0xfff;
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@ -2101,18 +2104,20 @@ def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
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// Tail calls.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
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def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
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def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
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Sched<[WriteBr]>;
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def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
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def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
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Sched<[WriteBr]>;
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def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
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4, IIC_Br, [],
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(Bcc br_target:$dst, (ops 14, zero_reg))>,
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Requires<[IsARM]>;
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Requires<[IsARM]>, Sched<[WriteBr]>;
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def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
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4, IIC_Br, [],
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(BX GPR:$dst)>,
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(BX GPR:$dst)>, Sched<[WriteBr]>,
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Requires<[IsARM]>;
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}
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@ -2126,7 +2131,8 @@ def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
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// Supervisor Call (Software Interrupt)
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let isCall = 1, Uses = [SP] in {
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def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
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def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
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Sched<[WriteBr]> {
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bits<24> svc;
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let Inst{23-0} = svc;
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}
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@ -4125,11 +4131,13 @@ let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
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def BCCi64 : PseudoInst<(outs),
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(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
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IIC_Br,
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[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
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[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
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Sched<[WriteBr]>;
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def BCCZi64 : PseudoInst<(outs),
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(ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
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[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
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[(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
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Sched<[WriteBr]>;
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} // usesCustomInserter
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@ -4834,7 +4842,7 @@ def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
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let isCall = 1,
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Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
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def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
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[(set R0, ARMthread_pointer)]>;
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[(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
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}
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//===----------------------------------------------------------------------===//
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@ -4898,7 +4906,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
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def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
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4, IIC_Br, [(brind GPR:$dst)],
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(MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
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Requires<[IsARM, NoV4T]>;
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Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
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// Large immediate handling.
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