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Teach the spiller to commute instructions in order to fold a reload. This hits 410 times on 444.namd and 122 times on 252.eon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52266 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
6100119620
commit
87bb991aa8
@ -36,16 +36,17 @@
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#include <algorithm>
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using namespace llvm;
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STATISTIC(NumSpills, "Number of register spills");
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STATISTIC(NumPSpills,"Number of physical register spills");
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STATISTIC(NumReMats, "Number of re-materialization");
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STATISTIC(NumDRM , "Number of re-materializable defs elided");
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STATISTIC(NumStores, "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumReused, "Number of values reused");
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STATISTIC(NumDSE , "Number of dead stores elided");
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STATISTIC(NumDCE , "Number of copies elided");
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STATISTIC(NumDSS , "Number of dead spill slots removed");
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STATISTIC(NumSpills , "Number of register spills");
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STATISTIC(NumPSpills ,"Number of physical register spills");
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STATISTIC(NumReMats , "Number of re-materialization");
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STATISTIC(NumDRM , "Number of re-materializable defs elided");
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STATISTIC(NumStores , "Number of stores added");
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STATISTIC(NumLoads , "Number of loads added");
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STATISTIC(NumReused , "Number of values reused");
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STATISTIC(NumDSE , "Number of dead stores elided");
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STATISTIC(NumDCE , "Number of copies elided");
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STATISTIC(NumDSS , "Number of dead spill slots removed");
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STATISTIC(NumCommutes, "Number of instructions commuted");
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namespace {
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enum SpillerName { simple, local };
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@ -356,6 +357,13 @@ namespace {
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AvailableSpills &Spills, BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM);
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bool CommuteToFoldReload(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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unsigned VirtReg, unsigned SrcReg, int SS,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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const TargetRegisterInfo *TRI,
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VirtRegMap &VRM);
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void SpillRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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int Idx, unsigned PhysReg, int StackSlot,
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@ -874,12 +882,12 @@ namespace {
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/// This enables unfolding optimization for a subsequent instruction which will
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/// also eliminate the newly introduced store instruction.
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bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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MachineBasicBlock::iterator &MII,
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std::vector<MachineInstr*> &MaybeDeadStores,
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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AvailableSpills &Spills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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MachineFunction &MF = *MBB.getParent();
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MachineInstr &MI = *MII;
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unsigned UnfoldedOpc = 0;
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@ -971,6 +979,97 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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return false;
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}
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/// CommuteToFoldReload -
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/// Look for
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/// r1 = load fi#1
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/// r1 = op r1, r2<kill>
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/// store r1, fi#1
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///
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/// If op is commutable and r2 is killed, then we can xform these to
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/// r2 = op r2, fi#1
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/// store r2, fi#1
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bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MII,
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unsigned VirtReg, unsigned SrcReg, int SS,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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const TargetRegisterInfo *TRI,
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VirtRegMap &VRM) {
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if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
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return false;
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MachineFunction &MF = *MBB.getParent();
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MachineInstr &MI = *MII;
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MachineBasicBlock::iterator DefMII = prior(MII);
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MachineInstr *DefMI = DefMII;
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const TargetInstrDesc &TID = DefMI->getDesc();
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unsigned NewDstIdx;
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if (DefMII != MBB.begin() &&
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TID.isCommutable() &&
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TII->CommuteChangesDestination(DefMI, NewDstIdx)) {
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MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
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unsigned NewReg = NewDstMO.getReg();
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if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
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return false;
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MachineInstr *ReloadMI = prior(DefMII);
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int FrameIdx;
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unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
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if (DestReg != SrcReg || FrameIdx != SS)
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return false;
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int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
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if (UseIdx == -1)
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return false;
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int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO);
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if (DefIdx == -1)
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return false;
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assert(DefMI->getOperand(DefIdx).isRegister() &&
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DefMI->getOperand(DefIdx).getReg() == SrcReg);
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// Now commute def instruction.
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MachineInstr *CommutedMI = TII->commuteInstruction(DefMI);
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if (!CommutedMI)
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return false;
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SmallVector<unsigned, 2> Ops;
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Ops.push_back(NewDstIdx);
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MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
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if (!FoldedMI) {
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if (CommutedMI == DefMI)
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TII->commuteInstruction(CommutedMI);
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else
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MBB.erase(CommutedMI);
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return false;
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}
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VRM.addSpillSlotUse(SS, FoldedMI);
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VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
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// Insert new def MI and spill MI.
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const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
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TII->storeRegToStackSlot(MBB, MI, NewReg, true, SS, RC);
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MII = prior(MII);
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MachineInstr *StoreMI = MII;
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VRM.addSpillSlotUse(SS, StoreMI);
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VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
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MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
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// Delete all 3 old instructions.
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InvalidateKills(MI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(&MI);
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MBB.erase(&MI);
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if (CommutedMI != DefMI)
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MBB.erase(CommutedMI);
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InvalidateKills(*DefMI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(DefMI);
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MBB.erase(DefMI);
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InvalidateKills(*ReloadMI, RegKills, KillOps);
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VRM.RemoveMachineInstrFromMaps(ReloadMI);
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MBB.erase(ReloadMI);
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++NumCommutes;
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return true;
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}
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return false;
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}
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/// findSuperReg - Find the SubReg's super-register of given register class
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/// where its SubIdx sub-register is SubReg.
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static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
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@ -1587,15 +1686,23 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
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assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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"Src hasn't been allocated yet?");
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if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
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RegKills, KillOps, TRI, VRM)) {
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NextMII = next(MII);
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BackTracked = true;
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goto ProcessNextInst;
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}
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// Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
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// this as a potentially dead store in case there is a subsequent
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// store into the stack slot without a read from it.
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MaybeDeadStores[StackSlot] = &MI;
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// If the stack slot value was previously available in some other
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// register, change it now. Otherwise, make the register available,
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// in PhysReg.
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Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
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// register, change it now. Otherwise, make the register
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// available in PhysReg.
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Spills.addAvailable(StackSlot, &MI, SrcReg, false/*!clobber*/);
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}
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}
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}
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42
test/CodeGen/X86/2008-06-13-SpillerCommuting.ll
Normal file
42
test/CodeGen/X86/2008-06-13-SpillerCommuting.ll
Normal file
@ -0,0 +1,42 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {spiller - Number of instructions commuted}
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%struct.CABAC_context_element = type { i8, i8 }
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%struct.MB_Info_CABAC = type { i8, i8, [2 x i8], i8, i8, i8, i16, i16, [4 x i8], [8 x %struct.MotionVector] }
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%struct.MotionVector = type { i16, i16 }
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%struct.RBSP2 = type { i32, i32, i16, i8, i16, i16, <1 x i64>, i32, i32, i32*, i32*, i32*, i32*, i32, i32, i32, i32, i32, i8, i16, i8, %struct.MB_Info_CABAC*, %struct.MB_Info_CABAC*, [2 x %struct.MB_Info_CABAC], [12 x i8], [460 x %struct.CABAC_context_element], [10 x i8], [10 x i8], [10 x i16], [4 x [120 x i32]], [15 x [36 x i8]], [6 x [8 x i8]], i16* }
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%struct.Slice_Info = type { i32, i8, %struct.seq_parameter_set_rbsp_t*, %struct.seq_parameter_set_rbsp_t, i32, i16*, i8, i8, i8, i8, i16, i32 }
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%struct.seq_parameter_set_rbsp_t = type { i32, i32, i32 }
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@_ZL21CABAC_CTX_state_table = external constant [64 x i16] ; <[64 x i16]*> [#uses=1]
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@_ZL15rLPS_table_64x4 = external constant [64 x [4 x i8]] ; <[64 x [4 x i8]]*> [#uses=1]
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define i32 @_ZN5RBSP220residual_block_cabacEP10Slice_InfoP13MB_Info_CABACS3_hjhhbPtPs(%struct.RBSP2* %this, %struct.Slice_Info* %slice, %struct.MB_Info_CABAC* %up, %struct.MB_Info_CABAC* %left, i8 zeroext %maxNumCoeff, i32 %blk_i, i8 zeroext %iCbCr, i8 zeroext %ctxBlockCat, i8 zeroext %intra_flag, i16* %mask, i16* %res) nounwind {
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entry:
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%tmp43.i1590 = getelementptr %struct.RBSP2* %this, i32 0, i32 0 ; <i32*> [#uses=1]
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br label %bb803
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bb803: ; preds = %_ZN5RBSP211decode_1bitEP21CABAC_context_element.exit1581, %entry
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%numCoeff.11749 = phi i32 [ 0, %entry ], [ %numCoeff.11749.tmp868, %_ZN5RBSP211decode_1bitEP21CABAC_context_element.exit1581 ] ; <i32> [#uses=1]
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%tmp28.i1503 = load i8* null, align 1 ; <i8> [#uses=1]
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%tmp30.i1504 = getelementptr %struct.RBSP2* %this, i32 0, i32 25, i32 0, i32 0 ; <i8*> [#uses=2]
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%tmp31.i1505 = load i8* %tmp30.i1504, align 1 ; <i8> [#uses=1]
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%tmp3233.i1506 = zext i8 %tmp31.i1505 to i32 ; <i32> [#uses=2]
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%tmp35.i1507 = getelementptr [64 x i16]* @_ZL21CABAC_CTX_state_table, i32 0, i32 %tmp3233.i1506 ; <i16*> [#uses=1]
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%tmp36.i1508 = load i16* %tmp35.i1507, align 2 ; <i16> [#uses=1]
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%tmp363738.i1509 = zext i16 %tmp36.i1508 to i32 ; <i32> [#uses=1]
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%tmp51.i1514 = getelementptr [64 x [4 x i8]]* @_ZL15rLPS_table_64x4, i32 0, i32 %tmp3233.i1506, i32 0 ; <i8*> [#uses=1]
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%tmp52.i1515 = load i8* %tmp51.i1514, align 1 ; <i8> [#uses=1]
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%tmp5758.i1516 = zext i8 %tmp52.i1515 to i32 ; <i32> [#uses=1]
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%tmp60.i1517 = sub i32 0, %tmp5758.i1516 ; <i32> [#uses=1]
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store i32 %tmp60.i1517, i32* %tmp43.i1590, align 16
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br i1 false, label %_ZN5RBSP211decode_1bitEP21CABAC_context_element.exit1581, label %bb.i1537
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bb.i1537: ; preds = %bb803
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unreachable
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_ZN5RBSP211decode_1bitEP21CABAC_context_element.exit1581: ; preds = %bb803
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%tmp328329.i1580 = trunc i32 %tmp363738.i1509 to i8 ; <i8> [#uses=1]
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store i8 %tmp328329.i1580, i8* %tmp30.i1504, align 1
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%toBool865 = icmp eq i8 %tmp28.i1503, 0 ; <i1> [#uses=1]
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%numCoeff.11749.tmp868 = select i1 %toBool865, i32 %numCoeff.11749, i32 0 ; <i32> [#uses=1]
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br label %bb803
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}
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