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R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224622 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
8cc9040b8e
commit
87bd2fa24b
@ -90,8 +90,9 @@ bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
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(AMDGPU::SSrc_64RegClassID == RegClass) ||
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(AMDGPU::VSrc_32RegClassID == RegClass) ||
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(AMDGPU::VSrc_64RegClassID == RegClass) ||
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(AMDGPU::VCSrc_32RegClassID == RegClass) ||
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(AMDGPU::VCSrc_64RegClassID == RegClass);
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(AMDGPU::VCSrc_32RegClassID == RegClass) ||
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(AMDGPU::VCSrc_64RegClassID == RegClass) ||
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(AMDGPU::SCSrc_32RegClassID == RegClass);
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}
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uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
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@ -1498,7 +1498,7 @@ multiclass MTBUF_Store_Helper <bits<3> op, string opName,
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op, opName, (outs),
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(ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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SReg_128:$srsrc, i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
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opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
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>;
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@ -1512,7 +1512,7 @@ multiclass MTBUF_Load_Helper <bits<3> op, string opName,
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op, opName, (outs regClass:$dst),
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(ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, SReg_128:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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i1imm:$slc, i1imm:$tfe, SCSrc_32:$soffset),
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opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
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#" $nfmt, $vaddr, $srsrc, $slc, $tfe, $soffset", []
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>;
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@ -1579,7 +1579,7 @@ multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
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def _OFFSET : MUBUFAtomicOffset <
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op, (outs),
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(ins rc:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
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SSrc_32:$soffset, slc:$slc),
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SCSrc_32:$soffset, slc:$slc),
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name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", []
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>, MUBUFAddr64Table<0>, AtomicNoRet<NAME#"_OFFSET", 0>;
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} // glc = 0
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@ -1601,7 +1601,7 @@ multiclass MUBUF_Atomic <bits<7> op, string name, RegisterClass rc,
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def _RTN_OFFSET : MUBUFAtomicOffset <
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op, (outs rc:$vdata),
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(ins rc:$vdata_in, SReg_128:$srsrc, mbuf_offset:$offset,
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SSrc_32:$soffset, slc:$slc),
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SCSrc_32:$soffset, slc:$slc),
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name#" $vdata, $srsrc, $soffset"#"$offset"#" glc $slc",
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[(set vt:$vdata,
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(atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset,
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@ -1624,7 +1624,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
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let offen = 0, idxen = 0, vaddr = 0 in {
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def _OFFSET : MUBUF_si <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc,
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mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
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mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
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slc:$slc, tfe:$tfe),
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asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
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[(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
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@ -1636,7 +1636,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
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let offen = 1, idxen = 0 in {
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def _OFFEN : MUBUF_si <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
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SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
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tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
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}
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@ -1644,7 +1644,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
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let offen = 0, idxen = 1 in {
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def _IDXEN : MUBUF_si <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
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mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
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slc:$slc, tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
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}
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@ -1652,7 +1652,7 @@ multiclass MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass,
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let offen = 1, idxen = 1 in {
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def _BOTHEN : MUBUF_si <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_64:$vaddr,
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SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
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}
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}
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@ -1675,7 +1675,7 @@ multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
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let offen = 0, idxen = 0, vaddr = 0 in {
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def _OFFSET : MUBUF_vi <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc,
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mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
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mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
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slc:$slc, tfe:$tfe),
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asm#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
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[(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc,
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@ -1687,7 +1687,7 @@ multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
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let offen = 1, idxen = 0 in {
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def _OFFEN : MUBUF_vi <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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SSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
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SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc,
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tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
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}
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@ -1695,7 +1695,7 @@ multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
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let offen = 0, idxen = 1 in {
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def _IDXEN : MUBUF_vi <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_32:$vaddr,
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mbuf_offset:$offset, SSrc_32:$soffset, glc:$glc,
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mbuf_offset:$offset, SCSrc_32:$soffset, glc:$glc,
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slc:$slc, tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>;
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}
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@ -1703,7 +1703,7 @@ multiclass MUBUF_Load_Helper_vi <bits<7> op, string asm, RegisterClass regClass,
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let offen = 1, idxen = 1 in {
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def _BOTHEN : MUBUF_vi <op, (outs regClass:$vdata),
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(ins SReg_128:$srsrc, VReg_64:$vaddr,
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SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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asm#" $vdata, $vaddr, $srsrc, $soffset, idxen offen"#"$glc"#"$slc"#"$tfe", []>;
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}
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}
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@ -1716,7 +1716,7 @@ multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass
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def "" : MUBUF_si <
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op, (outs),
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(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
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(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SCSrc_32:$soffset,
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mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc,
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tfe:$tfe),
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name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"#
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@ -1728,7 +1728,7 @@ multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass
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def _OFFSET : MUBUF_si <
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op, (outs),
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(ins vdataClass:$vdata, SReg_128:$srsrc, mbuf_offset:$offset,
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SSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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SCSrc_32:$soffset, glc:$glc, slc:$slc, tfe:$tfe),
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name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe",
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[(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset,
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i16:$offset, i1:$glc, i1:$slc,
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@ -1739,7 +1739,7 @@ multiclass MUBUF_Store_Helper <bits<7> op, string name, RegisterClass vdataClass
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let offen = 1, idxen = 0 in {
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def _OFFEN : MUBUF_si <
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op, (outs),
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(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SSrc_32:$soffset,
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(ins vdataClass:$vdata, SReg_128:$srsrc, VReg_32:$vaddr, SCSrc_32:$soffset,
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mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe),
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name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#
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"$glc"#"$slc"#"$tfe",
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@ -414,6 +414,7 @@ bool SIRegisterInfo::regClassCanUseInlineConstant(int RCID) const {
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default: return false;
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case AMDGPU::VCSrc_32RegClassID:
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case AMDGPU::VCSrc_64RegClassID:
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case AMDGPU::SCSrc_32RegClassID:
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return true;
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}
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}
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@ -221,6 +221,12 @@ def SSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
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def SSrc_64 : RegisterClass<"AMDGPU", [i64, f64, i1], 64, (add SReg_64)>;
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//===----------------------------------------------------------------------===//
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// SCSrc_* Operands with an SGPR or a inline constant
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//===----------------------------------------------------------------------===//
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def SCSrc_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add SReg_32)>;
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//===----------------------------------------------------------------------===//
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// VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
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//===----------------------------------------------------------------------===//
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@ -52,6 +52,45 @@ entry:
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ret void
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}
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; CHECK-LABEL: {{^}}soffset_max_imm:
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; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc
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define void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
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main_body:
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%tmp0 = getelementptr [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
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%tmp1 = load <16 x i8> addrspace(2)* %tmp0
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%tmp2 = shl i32 %6, 2
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%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
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%tmp4 = add i32 %6, 16
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%tmp5 = bitcast float 0.0 to i32
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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ret void
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}
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; Make sure immediates that aren't inline constants don't get folded into
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; the soffset operand.
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; FIXME: for this test we should be smart enough to shift the immediate into
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; the offset field.
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; CHECK-LABEL: {{^}}soffset_no_fold:
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; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41
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; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc
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define void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 {
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main_body:
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%tmp0 = getelementptr [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0
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%tmp1 = load <16 x i8> addrspace(2)* %tmp0
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%tmp2 = shl i32 %6, 2
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%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
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%tmp4 = add i32 %6, 16
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%tmp5 = bitcast float 0.0 to i32
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call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
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ret void
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}
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declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #3
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declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)
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attributes #1 = { "ShaderType"="2" "unsafe-fp-math"="true" }
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attributes #3 = { nounwind readonly }
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;;;==========================================================================;;;
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;;; MUBUF STORE TESTS
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;;;==========================================================================;;;
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