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Fix PR3934 part 2. findOnlyInterestingUse() was not setting IsCopy and IsDstPhys which are returned by value and used by callee. This happened to work on the earlier test cases because of a logic error in the caller side.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69006 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-04-14 00:32:25 +00:00
parent 4cbb173d6c
commit 87d696a4d2
3 changed files with 29 additions and 10 deletions
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18
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -405,7 +405,7 @@ static
MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
MachineRegisterInfo *MRI,
const TargetInstrInfo *TII,
bool &isCopy,
bool &IsCopy,
unsigned &DstReg, bool &IsDstPhys) {
MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
if (UI == MRI->use_end())
@ -418,11 +418,15 @@ MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
return 0;
unsigned SrcReg;
bool IsSrcPhys;
if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
IsCopy = true;
return &UseMI;
}
IsDstPhys = false;
if (isTwoAddrUse(UseMI, Reg, DstReg))
if (isTwoAddrUse(UseMI, Reg, DstReg)) {
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
return &UseMI;
}
return 0;
}
@ -634,12 +638,12 @@ void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
"Can't map to two src physical registers!");
SmallVector<unsigned, 4> VirtRegPairs;
bool isCopy = false;
bool IsCopy = false;
unsigned NewReg = 0;
while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
isCopy, NewReg, IsDstPhys)) {
if (isCopy) {
if (Processed.insert(UseMI))
IsCopy, NewReg, IsDstPhys)) {
if (IsCopy) {
if (!Processed.insert(UseMI))
break;
}

15
test/CodeGen/X86/2009-04-13-2AddrAssert-2.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin
; rdar://6781755
; PR3934
type { i32, i32 } ; type %0
define void @bn_sqr_comba8(i32* nocapture %r, i32* %a) nounwind {
entry:
%asmtmp23 = tail call %0 asm "mulq $3", "={ax},={dx},{ax},*m,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32* %a) nounwind ; <%0> [#uses=1]
%asmresult25 = extractvalue %0 %asmtmp23, 1 ; <i32> [#uses=1]
%asmtmp26 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={dx},=r,imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 %asmresult25, i32 0) nounwind ; <%0> [#uses=1]
%asmresult27 = extractvalue %0 %asmtmp26, 0 ; <i32> [#uses=1]
%asmtmp29 = tail call %0 asm "addq $0,$0; adcq $2,$1", "={ax},={dx},imr,0,1,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 0, i32 0, i32 %asmresult27) nounwind ; <%0> [#uses=0]
ret void
}

2
test/CodeGen/X86/subreg-to-reg-1.ll
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@ -5,7 +5,7 @@
; though this isn't necessary; The point of this test is to make sure
; a 32-bit add is used.
define i64 @foo(i64 %a) {
define i64 @foo(i64 %a) nounwind {
%b = add i64 %a, 4294967295
%c = and i64 %b, 4294967295
%d = add i64 %c, 1