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Added a few tweaks to the Intel Descriptor-table support instructions to allow

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word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2010-10-19 00:01:44 +00:00
parent 70987fbc60
commit 87f4a1a433
4 changed files with 128 additions and 0 deletions
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40
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -1089,6 +1089,46 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc));
}
// "lgdtl" is not ambiguous 32-bit mode and is the same as "lgdt".
// "lgdtq" is not ambiguous 64-bit mode and is the same as "lgdt".
if ((Name == "lgdtl" && Is64Bit == false) ||
(Name == "lgdtq" && Is64Bit == true)) {
const char *NewName = "lgdt";
delete Operands[0];
Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
Name = NewName;
}
// "lidtl" is not ambiguous 32-bit mode and is the same as "lidt".
// "lidtq" is not ambiguous 64-bit mode and is the same as "lidt".
if ((Name == "lidtl" && Is64Bit == false) ||
(Name == "lidtq" && Is64Bit == true)) {
const char *NewName = "lidt";
delete Operands[0];
Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
Name = NewName;
}
// "sgdtl" is not ambiguous 32-bit mode and is the same as "sgdt".
// "sgdtq" is not ambiguous 64-bit mode and is the same as "sgdt".
if ((Name == "sgdtl" && Is64Bit == false) ||
(Name == "sgdtq" && Is64Bit == true)) {
const char *NewName = "sgdt";
delete Operands[0];
Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
Name = NewName;
}
// "sidtl" is not ambiguous 32-bit mode and is the same as "sidt".
// "sidtq" is not ambiguous 64-bit mode and is the same as "sidt".
if ((Name == "sidtl" && Is64Bit == false) ||
(Name == "sidtq" && Is64Bit == true)) {
const char *NewName = "sidt";
delete Operands[0];
Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
Name = NewName;
}
return false;
}

8
lib/Target/X86/X86InstrSystem.td
View File

@ -321,8 +321,12 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
//===----------------------------------------------------------------------===//
// Descriptor-table support instructions
def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
"sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
"sgdt\t$dst", []>, TB;
def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
"sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
"sidt\t$dst", []>, TB;
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
@ -339,8 +343,12 @@ def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
"sldt{q}\t$dst", []>, TB;
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
"lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
"lgdt\t$src", []>, TB;
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
"lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
"lidt\t$src", []>, TB;
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),

48
test/MC/X86/x86-32.s
View File

@ -654,3 +654,51 @@ pshufw $90, %mm4, %mm0
// CHECK: arpl %bx, 6(%ecx)
// CHECK: encoding: [0x63,0x59,0x06]
arpl %bx,6(%ecx)
// CHECK: lgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x50,0x04]
lgdtw 4(%eax)
// CHECK: lgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdt 4(%eax)
// CHECK: lgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdtl 4(%eax)
// CHECK: lidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x58,0x04]
lidtw 4(%eax)
// CHECK: lidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidt 4(%eax)
// CHECK: lidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidtl 4(%eax)
// CHECK: sgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x40,0x04]
sgdtw 4(%eax)
// CHECK: sgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdt 4(%eax)
// CHECK: sgdt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdtl 4(%eax)
// CHECK: sidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x48,0x04]
sidtw 4(%eax)
// CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidt 4(%eax)
// CHECK: sidt 4(%eax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtl 4(%eax)

32
test/MC/X86/x86-64.s
View File

@ -795,3 +795,35 @@ decb %al // CHECK: decb %al # encoding: [0xfe,0xc8]
decw %ax // CHECK: decw %ax # encoding: [0x66,0xff,0xc8]
decl %eax // CHECK: decl %eax # encoding: [0xff,0xc8]
// rdar://8416805
// CHECK: lgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdt 4(%rax)
// CHECK: lgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdtq 4(%rax)
// CHECK: lidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidt 4(%rax)
// CHECK: lidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidtq 4(%rax)
// CHECK: sgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdt 4(%rax)
// CHECK: sgdt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdtq 4(%rax)
// CHECK: sidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidt 4(%rax)
// CHECK: sidt 4(%rax)
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtq 4(%rax)