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Use a command-line option to turn register scavenging on/off for PPC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2008-03-04 23:13:51 +00:00
parent 6494768ffc
commit 880d0f6018
2 changed files with 51 additions and 39 deletions
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15
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -19,8 +19,11 @@
#include "PPCTargetMachine.h" #include "PPCTargetMachine.h"
#include "llvm/ADT/STLExtras.h" #include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/CommandLine.h"
using namespace llvm; using namespace llvm;
extern cl::opt<bool> EnablePPCRS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
: TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
RI(*TM.getSubtargetImpl(), *this) {} RI(*TM.getSubtargetImpl(), *this) {}
@ -320,8 +323,7 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
static bool StoreRegToStackSlot(const TargetInstrInfo &TII, static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
unsigned SrcReg, bool isKill, int FrameIdx, unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs, SmallVectorImpl<MachineInstr*> &NewMIs) {
bool isPPC64/*FIXME (64-bit): Remove.*/) {
if (RC == PPC::GPRCRegisterClass) { if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) { if (SrcReg != PPC::LR) {
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW)) NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
@ -353,7 +355,7 @@ static bool StoreRegToStackSlot(const TargetInstrInfo &TII,
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS)) NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
.addReg(SrcReg, false, false, isKill), FrameIdx)); .addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) { } else if (RC == PPC::CRRCRegisterClass) {
if (!isPPC64) { // FIXME (64-bit): Enable if (EnablePPCRS) { // FIXME (64-bit): Enable
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR)) NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill), .addReg(SrcReg, false, false, isKill),
FrameIdx)); FrameIdx));
@ -402,8 +404,7 @@ PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
const TargetRegisterClass *RC) const { const TargetRegisterClass *RC) const {
SmallVector<MachineInstr*, 4> NewMIs; SmallVector<MachineInstr*, 4> NewMIs;
if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs, if (StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) {
PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>(); PPCFunctionInfo *FuncInfo = MBB.getParent()->getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR(); FuncInfo->setSpillsCR();
} }
@ -418,8 +419,8 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{ SmallVectorImpl<MachineInstr*> &NewMIs) const{
if (Addr[0].isFrameIndex()) { if (Addr[0].isFrameIndex()) {
if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs, if (StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(),
TM.getSubtargetImpl()->isPPC64()/*FIXME (64-bit): Remove.*/)) { RC, NewMIs)) {
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR(); FuncInfo->setSpillsCR();
} }

29
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -42,10 +42,16 @@
#include <cstdlib> #include <cstdlib>
using namespace llvm; using namespace llvm;
// FIXME (64-bit): Eventually enable by default.
cl::opt<bool> EnablePPCRS("enable-ppc-regscavenger",
cl::init(false),
cl::desc("enable PPC register scavenger"),
cl::Hidden);
// FIXME (64-bit): Should be inlined. // FIXME (64-bit): Should be inlined.
bool bool
PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const { PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
return !Subtarget.isPPC64(); return EnablePPCRS;
} }
/// getRegisterNumbering - Given the enum value for some register, e.g. /// getRegisterNumbering - Given the enum value for some register, e.g.
@ -310,6 +316,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
Reserved.set(PPC::R13); Reserved.set(PPC::R13);
Reserved.set(PPC::R31); Reserved.set(PPC::R31);
if (!EnablePPCRS)
Reserved.set(PPC::R0); // FIXME (64-bit): Remove Reserved.set(PPC::R0); // FIXME (64-bit): Remove
Reserved.set(PPC::X0); Reserved.set(PPC::X0);
@ -414,7 +421,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
// FIXME (64-bit): Use "findScratchRegister" // FIXME (64-bit): Use "findScratchRegister"
unsigned Reg; unsigned Reg;
if (!LP64) if (EnablePPCRS)
Reg = findScratchRegister(II, RS, RC, SPAdj); Reg = findScratchRegister(II, RS, RC, SPAdj);
else else
Reg = PPC::R0; Reg = PPC::R0;
@ -424,10 +431,15 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
.addReg(PPC::R31) .addReg(PPC::R31)
.addImm(FrameSize); .addImm(FrameSize);
} else if (LP64) { } else if (LP64) {
Reg = PPC::X0; // FIXME (64-bit): Remove. if (!EnablePPCRS)
if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
BuildMI(MBB, II, TII.get(PPC::LD), Reg) BuildMI(MBB, II, TII.get(PPC::LD), Reg)
.addImm(0) .addImm(0)
.addReg(PPC::X1); .addReg(PPC::X1);
else
BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
.addImm(0)
.addReg(PPC::X1);
} else { } else {
BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
.addImm(0) .addImm(0)
@ -437,17 +449,16 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
// Grow the stack and update the stack pointer link, then determine the // Grow the stack and update the stack pointer link, then determine the
// address of new allocated space. // address of new allocated space.
if (LP64) { if (LP64) {
#if 0 // FIXME (64-bit): Enable if (EnablePPCRS) // FIXME (64-bit): Use "true" version.
BuildMI(MBB, II, TII.get(PPC::STDUX)) BuildMI(MBB, II, TII.get(PPC::STDUX))
.addReg(Reg, false, false, true) .addReg(Reg, false, false, true)
.addReg(PPC::X1) .addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
#else else
BuildMI(MBB, II, TII.get(PPC::STDUX)) BuildMI(MBB, II, TII.get(PPC::STDUX))
.addReg(PPC::X0, false, false, true) .addReg(PPC::X0, false, false, true)
.addReg(PPC::X1) .addReg(PPC::X1)
.addReg(MI.getOperand(1).getReg()); .addReg(MI.getOperand(1).getReg());
#endif
if (!MI.getOperand(1).isKill()) if (!MI.getOperand(1).isKill())
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
@ -573,7 +584,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
} }
// Special case for pseudo-op SPILL_CR. // Special case for pseudo-op SPILL_CR.
if (!Subtarget.isPPC64()) // FIXME (64-bit): Remove. if (EnablePPCRS) // FIXME (64-bit): Enable by default
if (OpC == PPC::SPILL_CR) { if (OpC == PPC::SPILL_CR) {
lowerCRSpilling(II, FrameIndex, SPAdj, RS); lowerCRSpilling(II, FrameIndex, SPAdj, RS);
return; return;
@ -627,7 +638,7 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// FIXME (64-bit): Use "findScratchRegister". // FIXME (64-bit): Use "findScratchRegister".
unsigned SReg; unsigned SReg;
if (!Subtarget.isPPC64()) if (EnablePPCRS)
SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj); SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
else else
SReg = PPC::R0; SReg = PPC::R0;
@ -879,7 +890,7 @@ PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// FIXME: doesn't detect whether or not we need to spill vXX, which requires // FIXME: doesn't detect whether or not we need to spill vXX, which requires
// r0 for now. // r0 for now.
if (!IsPPC64) // FIXME (64-bit): Enable. if (EnablePPCRS) // FIXME (64-bit): Enable.
if (needsFP(MF) || spillsCR(MF)) { if (needsFP(MF) || spillsCR(MF)) {
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;