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[mips] [IAS] Add support for generating DADDu to createAddu(). NFC.

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Summary: This isn't used right now, but it will be in some upcoming changes.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10568

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240407 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu 2015-06-23 14:00:54 +00:00
parent 9758b4ae95
commit 88278a22cc
1 changed files with 7 additions and 7 deletions
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14
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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@ -218,7 +218,7 @@ class MipsAsmParser : public MCTargetAsmParser {
SmallVectorImpl<MCInst> &Instructions); SmallVectorImpl<MCInst> &Instructions);
void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg,
SmallVectorImpl<MCInst> &Instructions); bool Is64Bit, SmallVectorImpl<MCInst> &Instructions);
bool reportParseError(Twine ErrorMsg); bool reportParseError(Twine ErrorMsg);
bool reportParseError(SMLoc Loc, Twine ErrorMsg); bool reportParseError(SMLoc Loc, Twine ErrorMsg);
@ -1836,7 +1836,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
createLShiftOri<0>(Bits15To0, TmpReg, IDLoc, Instructions); createLShiftOri<0>(Bits15To0, TmpReg, IDLoc, Instructions);
if (UseSrcReg) if (UseSrcReg)
createAddu(DstReg, TmpReg, SrcReg, Instructions); createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
} else if ((ImmValue & (0xffffLL << 48)) == 0) { } else if ((ImmValue & (0xffffLL << 48)) == 0) {
if (Is32BitImm) { if (Is32BitImm) {
@ -1870,7 +1870,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
createLShiftOri<16>(Bits15To0, TmpReg, IDLoc, Instructions); createLShiftOri<16>(Bits15To0, TmpReg, IDLoc, Instructions);
if (UseSrcReg) if (UseSrcReg)
createAddu(DstReg, TmpReg, SrcReg, Instructions); createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
} else { } else {
if (Is32BitImm) { if (Is32BitImm) {
@ -1914,7 +1914,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg,
} }
if (UseSrcReg) if (UseSrcReg)
createAddu(DstReg, TmpReg, SrcReg, Instructions); createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions);
} }
return false; return false;
} }
@ -2051,7 +2051,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress(
} }
if (UseSrcReg) if (UseSrcReg)
createAddu(DstReg, TmpReg, SrcReg, Instructions); createAddu(DstReg, TmpReg, SrcReg, !Is32BitSym, Instructions);
return false; return false;
} }
@ -2488,10 +2488,10 @@ void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
} }
void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg, void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg,
unsigned TrgReg, unsigned TrgReg, bool Is64Bit,
SmallVectorImpl<MCInst> &Instructions) { SmallVectorImpl<MCInst> &Instructions) {
MCInst AdduInst; MCInst AdduInst;
AdduInst.setOpcode(Mips::ADDu); AdduInst.setOpcode(Is64Bit ? Mips::DADDu : Mips::ADDu);
AdduInst.addOperand(MCOperand::createReg(DstReg)); AdduInst.addOperand(MCOperand::createReg(DstReg));
AdduInst.addOperand(MCOperand::createReg(SrcReg)); AdduInst.addOperand(MCOperand::createReg(SrcReg));
AdduInst.addOperand(MCOperand::createReg(TrgReg)); AdduInst.addOperand(MCOperand::createReg(TrgReg));