mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-09 01:38:03 +00:00
R600/SI: Remove stray debug statements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227462 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
51a3c27d6e
commit
882d1b71e0
@ -23,7 +23,6 @@
|
||||
#include "llvm/IR/Function.h"
|
||||
#include "llvm/IR/LLVMContext.h"
|
||||
|
||||
#include "llvm/Support/Debug.h"
|
||||
using namespace llvm;
|
||||
|
||||
SIRegisterInfo::SIRegisterInfo(const AMDGPUSubtarget &st)
|
||||
@ -140,7 +139,6 @@ void SIRegisterInfo::buildScratchLoadStore(MachineBasicBlock::iterator MI,
|
||||
unsigned Size = NumSubRegs * 4;
|
||||
|
||||
if (!isUInt<12>(Offset + Size)) {
|
||||
dbgs() << "Offset scavenge\n";
|
||||
SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
|
||||
if (SOffset == AMDGPU::NoRegister) {
|
||||
RanOutOfSGPRs = true;
|
||||
@ -235,10 +233,8 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
|
||||
Ctx.emitError("Ran out of VGPRs for spilling SGPR");
|
||||
}
|
||||
|
||||
if (isM0) {
|
||||
dbgs() << "Scavenge M0\n";
|
||||
if (isM0)
|
||||
SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
|
||||
}
|
||||
|
||||
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
|
||||
.addReg(Spill.VGPR)
|
||||
|
Loading…
x
Reference in New Issue
Block a user