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Expand all atomic ops for mips16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166935 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -212,8 +212,14 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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if (Subtarget->inMips16Mode()) {
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
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}
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else {
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
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}
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if (!Subtarget->inMips16Mode()) {
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if (!Subtarget->inMips16Mode()) {
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::LOAD, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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@ -320,6 +326,21 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
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if (Subtarget->inMips16Mode()) {
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
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}
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setInsertFencesForAtomic(true);
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setInsertFencesForAtomic(true);
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if (!Subtarget->hasSEInReg()) {
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if (!Subtarget->hasSEInReg()) {
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40
test/CodeGen/Mips/atomicops.ll
Normal file
40
test/CodeGen/Mips/atomicops.ll
Normal file
@ -0,0 +1,40 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1
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define i32 @foo(i32* %mem, i32 %val, i32 %c) nounwind {
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entry:
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%0 = atomicrmw add i32* %mem, i32 %val seq_cst
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%add = add nsw i32 %0, %c
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ret i32 %add
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; 16: foo:
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; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
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}
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define i32 @main() nounwind {
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entry:
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%x = alloca i32, align 4
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store volatile i32 0, i32* %x, align 4
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%0 = atomicrmw add i32* %x, i32 1 seq_cst
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%add.i = add nsw i32 %0, 2
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%1 = load volatile i32* %x, align 4
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%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %add.i, i32 %1) nounwind
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%2 = cmpxchg i32* %x, i32 1, i32 2 seq_cst
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%3 = load volatile i32* %x, align 4
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%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %2, i32 %3) nounwind
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%4 = atomicrmw xchg i32* %x, i32 1 seq_cst
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%5 = load volatile i32* %x, align 4
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%call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
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; 16: main:
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; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
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; 16: lw ${{[0-9]+}}, %call16(__sync_lock_test_and_set_4)(${{[0-9]+}})
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ret i32 0
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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