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Indexed load / store changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31208 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -314,7 +314,8 @@ public:
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SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
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SDOperand Chain, SDOperand Ptr, const Value *SV,
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int SVOffset, MVT::ValueType EVT, bool isVolatile=false);
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SDOperand getPreIndexedLoad(SDOperand OrigLoad, SDOperand Base);
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SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
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SDOperand Offset, ISD::MemOpAddrMode AM);
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SDOperand getVecLoad(unsigned Count, MVT::ValueType VT, SDOperand Chain,
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SDOperand Ptr, SDOperand SV);
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@ -370,9 +370,10 @@ namespace ISD {
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// operations.
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FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI,
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// Other operators. LOAD and STORE have token chains as their first
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// operand, then the same operands as an LLVM load/store instruction, then a
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// SRCVALUE node that provides alias analysis information.
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// LOAD and STORE have token chains as their first operand, then the same
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// operands as an LLVM load/store instruction, then an offset node that
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// is added / subtracted from the base pointer to form the address (for
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// indexed memory ops).
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LOAD, STORE,
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// Abstract vector version of LOAD. VLOAD has a constant element count as
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@ -529,8 +530,8 @@ namespace ISD {
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/// load); an unindexed store does not produces a value.
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///
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/// PRE_INC Similar to the unindexed mode where the effective address is
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/// PRE_DEC the result of computation of the base pointer. However, it
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/// considers the computation as being folded into the load /
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/// PRE_DEC the value of the base pointer add / subtract the offset.
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/// It considers the computation as being folded into the load /
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/// store operation (i.e. the load / store does the address
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/// computation as well as performing the memory transaction).
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/// The base operand is always undefined. In addition to
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@ -540,12 +541,12 @@ namespace ISD {
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/// of the address computation).
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///
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/// POST_INC The effective address is the value of the base pointer. The
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/// POST_DEC value of the offset operand is then added to the base after
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/// memory transaction. In addition to producing a chain,
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/// post-indexed load produces two values (the result of the load
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/// and the result of the base + offset computation); a
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/// post-indexed store produces one value (the the result of the
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/// base + offset computation).
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/// POST_DEC value of the offset operand is then added to / subtracted
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/// from the base after memory transaction. In addition to
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/// producing a chain, post-indexed load produces two values
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/// (the result of the load and the result of the base +/- offset
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/// computation); a post-indexed store produces one value (the
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/// the result of the base +/- offset computation).
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///
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enum MemOpAddrMode {
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UNINDEXED = 0,
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@ -1408,9 +1409,8 @@ protected:
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: SDNode(ISD::LOAD, Chain, Ptr, Off),
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AddrMode(AM), ExtType(ETy), LoadedVT(LVT), SrcValue(SV), SVOffset(O),
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Alignment(Align), IsVolatile(Vol) {
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assert((Off.getOpcode() == ISD::UNDEF ||
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AddrMode == ISD::POST_INC || AddrMode == ISD::POST_DEC) &&
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"Only post-indexed load has a non-undef offset operand");
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assert((Off.getOpcode() == ISD::UNDEF || AddrMode != ISD::UNINDEXED) &&
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"Only indexed load has a non-undef offset operand");
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}
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public:
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@ -1462,9 +1462,8 @@ protected:
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: SDNode(ISD::STORE, Chain, Value, Ptr, Off),
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AddrMode(AM), IsTruncStore(isTrunc), StoredVT(SVT), SrcValue(SV),
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SVOffset(O), Alignment(Align), IsVolatile(Vol) {
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assert((Off.getOpcode() == ISD::UNDEF ||
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AddrMode == ISD::POST_INC || AddrMode == ISD::POST_DEC) &&
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"Only post-indexed store has a non-undef offset operand");
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assert((Off.getOpcode() == ISD::UNDEF || AddrMode != ISD::UNINDEXED) &&
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"Only indexed store has a non-undef offset operand");
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}
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public:
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