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eliminateFrameIndex() bug when frame pointer is used as base register.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33945 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-02-06 00:23:31 +00:00
parent ad0e465889
commit 88b633165a
1 changed files with 27 additions and 23 deletions
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50
lib/Target/ARM/ARMRegisterInfo.cpp
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@@ -386,6 +386,8 @@ void emitThumbRegPlusConstPool(MachineBasicBlock &MBB,
const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg); const MachineInstrBuilder MIB = BuildMI(MBB, MBBI, TII.get(Opc), DestReg);
if (DestReg == ARM::SP) if (DestReg == ARM::SP)
MIB.addReg(BaseReg).addReg(LdReg); MIB.addReg(BaseReg).addReg(LdReg);
else if (isSub)
MIB.addReg(BaseReg).addReg(LdReg);
else else
MIB.addReg(LdReg).addReg(BaseReg); MIB.addReg(LdReg).addReg(BaseReg);
if (DestReg == ARM::SP) if (DestReg == ARM::SP)
@@ -647,7 +649,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
// MI would expand into a large number of instructions. Don't try to // MI would expand into a large number of instructions. Don't try to
// simplify the immediate. // simplify the immediate.
if (NumMIs > 2) { if (NumMIs > 2) {
emitThumbRegPlusImmediate(MBB, II, DestReg, ARM::SP, Offset, TII); emitThumbRegPlusImmediate(MBB, II, DestReg, FrameReg, Offset, TII);
MBB.erase(II); MBB.erase(II);
return; return;
} }
@@ -705,7 +707,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
case ARMII::AddrModeTs: { case ARMII::AddrModeTs: {
ImmIdx = i+1; ImmIdx = i+1;
InstrOffs = MI.getOperand(ImmIdx).getImm(); InstrOffs = MI.getOperand(ImmIdx).getImm();
NumBits = 8; NumBits = (FrameReg == ARM::SP) ? 8 : 5;
Scale = 4; Scale = 4;
break; break;
} }
@@ -722,31 +724,33 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
isSub = true; isSub = true;
} }
MachineOperand &ImmOp = MI.getOperand(ImmIdx); if (!isSub || !isThumb) {
int ImmedOffset = Offset / Scale; MachineOperand &ImmOp = MI.getOperand(ImmIdx);
unsigned Mask = (1 << NumBits) - 1; int ImmedOffset = Offset / Scale;
if ((unsigned)Offset <= Mask * Scale) { unsigned Mask = (1 << NumBits) - 1;
// Replace the FrameIndex with sp if ((unsigned)Offset <= Mask * Scale) {
MI.getOperand(i).ChangeToRegister(FrameReg, false); // Replace the FrameIndex with sp
MI.getOperand(i).ChangeToRegister(FrameReg, false);
if (isSub)
ImmedOffset |= 1 << NumBits;
ImmOp.ChangeToImmediate(ImmedOffset);
return;
}
// Otherwise, it didn't fit. Pull in what we can to simplify the immed.
if (AddrMode == ARMII::AddrModeTs) {
// Thumb tLDRspi, tSTRspi. These will change to instructions that use
// a different base register.
NumBits = 5;
Mask = (1 << NumBits) - 1;
}
ImmedOffset = ImmedOffset & Mask;
if (isSub) if (isSub)
ImmedOffset |= 1 << NumBits; ImmedOffset |= 1 << NumBits;
ImmOp.ChangeToImmediate(ImmedOffset); ImmOp.ChangeToImmediate(ImmedOffset);
return; Offset &= ~(Mask*Scale);
} }
// Otherwise, it didn't fit. Pull in what we can to simplify the immediate.
if (AddrMode == ARMII::AddrModeTs) {
// Thumb tLDRspi, tSTRspi. These will change to instructions that use a
// different base register.
NumBits = 5;
Mask = (1 << NumBits) - 1;
}
ImmedOffset = ImmedOffset & Mask;
if (isSub)
ImmedOffset |= 1 << NumBits;
ImmOp.ChangeToImmediate(ImmedOffset);
Offset &= ~(Mask*Scale);
} }
// If we get here, the immediate doesn't fit into the instruction. We folded // If we get here, the immediate doesn't fit into the instruction. We folded