mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable us to match the TargetMachine for our TargetRegisterInfo classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
7385cafb7a
commit
88d724909e
@ -1991,7 +1991,7 @@ ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
|
|||||||
if (isCalleeStructRet || isCallerStructRet)
|
if (isCalleeStructRet || isCallerStructRet)
|
||||||
return false;
|
return false;
|
||||||
|
|
||||||
// FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
|
// FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
|
||||||
// emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
|
// emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
|
||||||
// the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
|
// the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
|
||||||
// support in the assembler and linker to be used. This would need to be
|
// support in the assembler and linker to be used. This would need to be
|
||||||
|
@ -19,7 +19,7 @@
|
|||||||
#include "ARMMachineFunctionInfo.h"
|
#include "ARMMachineFunctionInfo.h"
|
||||||
#include "ARMSubtarget.h"
|
#include "ARMSubtarget.h"
|
||||||
#include "MCTargetDesc/ARMAddressingModes.h"
|
#include "MCTargetDesc/ARMAddressingModes.h"
|
||||||
#include "Thumb1RegisterInfo.h"
|
#include "ThumbRegisterInfo.h"
|
||||||
#include "llvm/ADT/DenseMap.h"
|
#include "llvm/ADT/DenseMap.h"
|
||||||
#include "llvm/ADT/STLExtras.h"
|
#include "llvm/ADT/STLExtras.h"
|
||||||
#include "llvm/ADT/SmallPtrSet.h"
|
#include "llvm/ADT/SmallPtrSet.h"
|
||||||
|
@ -40,10 +40,9 @@ add_llvm_target(ARMCodeGen
|
|||||||
MLxExpansionPass.cpp
|
MLxExpansionPass.cpp
|
||||||
Thumb1FrameLowering.cpp
|
Thumb1FrameLowering.cpp
|
||||||
Thumb1InstrInfo.cpp
|
Thumb1InstrInfo.cpp
|
||||||
Thumb1RegisterInfo.cpp
|
ThumbRegisterInfo.cpp
|
||||||
Thumb2ITBlockPass.cpp
|
Thumb2ITBlockPass.cpp
|
||||||
Thumb2InstrInfo.cpp
|
Thumb2InstrInfo.cpp
|
||||||
Thumb2RegisterInfo.cpp
|
|
||||||
Thumb2SizeReduction.cpp
|
Thumb2SizeReduction.cpp
|
||||||
)
|
)
|
||||||
|
|
||||||
|
@ -232,7 +232,7 @@ Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
|
|||||||
//===---------------------------------------------------------------------===//
|
//===---------------------------------------------------------------------===//
|
||||||
|
|
||||||
Thumb1 immediate field sometimes keep pre-scaled values. See
|
Thumb1 immediate field sometimes keep pre-scaled values. See
|
||||||
Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
|
ThumbRegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
|
||||||
Thumb2.
|
Thumb2.
|
||||||
|
|
||||||
//===---------------------------------------------------------------------===//
|
//===---------------------------------------------------------------------===//
|
||||||
|
@ -41,7 +41,7 @@ static void
|
|||||||
emitSPUpdate(MachineBasicBlock &MBB,
|
emitSPUpdate(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator &MBBI,
|
MachineBasicBlock::iterator &MBBI,
|
||||||
const TargetInstrInfo &TII, DebugLoc dl,
|
const TargetInstrInfo &TII, DebugLoc dl,
|
||||||
const Thumb1RegisterInfo &MRI,
|
const ThumbRegisterInfo &MRI,
|
||||||
int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
|
int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) {
|
||||||
emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
|
emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
|
||||||
MRI, MIFlags);
|
MRI, MIFlags);
|
||||||
@ -53,8 +53,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|||||||
MachineBasicBlock::iterator I) const {
|
MachineBasicBlock::iterator I) const {
|
||||||
const Thumb1InstrInfo &TII =
|
const Thumb1InstrInfo &TII =
|
||||||
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
||||||
const Thumb1RegisterInfo *RegInfo =
|
const ThumbRegisterInfo *RegInfo =
|
||||||
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
|
static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
|
||||||
if (!hasReservedCallFrame(MF)) {
|
if (!hasReservedCallFrame(MF)) {
|
||||||
// If we have alloca, convert as follows:
|
// If we have alloca, convert as follows:
|
||||||
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
||||||
@ -89,8 +89,8 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const {
|
|||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
MachineModuleInfo &MMI = MF.getMMI();
|
MachineModuleInfo &MMI = MF.getMMI();
|
||||||
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
|
const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
|
||||||
const Thumb1RegisterInfo *RegInfo =
|
const ThumbRegisterInfo *RegInfo =
|
||||||
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
|
static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
|
||||||
const Thumb1InstrInfo &TII =
|
const Thumb1InstrInfo &TII =
|
||||||
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
||||||
|
|
||||||
@ -327,8 +327,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
|
|||||||
DebugLoc dl = MBBI->getDebugLoc();
|
DebugLoc dl = MBBI->getDebugLoc();
|
||||||
MachineFrameInfo *MFI = MF.getFrameInfo();
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
const Thumb1RegisterInfo *RegInfo =
|
const ThumbRegisterInfo *RegInfo =
|
||||||
static_cast<const Thumb1RegisterInfo *>(STI.getRegisterInfo());
|
static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
|
||||||
const Thumb1InstrInfo &TII =
|
const Thumb1InstrInfo &TII =
|
||||||
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
*static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
|
||||||
|
|
||||||
|
@ -16,7 +16,7 @@
|
|||||||
|
|
||||||
#include "ARMFrameLowering.h"
|
#include "ARMFrameLowering.h"
|
||||||
#include "Thumb1InstrInfo.h"
|
#include "Thumb1InstrInfo.h"
|
||||||
#include "Thumb1RegisterInfo.h"
|
#include "ThumbRegisterInfo.h"
|
||||||
#include "llvm/Target/TargetFrameLowering.h"
|
#include "llvm/Target/TargetFrameLowering.h"
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
|
@ -15,13 +15,13 @@
|
|||||||
#define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
|
#define LLVM_LIB_TARGET_ARM_THUMB1INSTRINFO_H
|
||||||
|
|
||||||
#include "ARMBaseInstrInfo.h"
|
#include "ARMBaseInstrInfo.h"
|
||||||
#include "Thumb1RegisterInfo.h"
|
#include "ThumbRegisterInfo.h"
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
|
|
||||||
class Thumb1InstrInfo : public ARMBaseInstrInfo {
|
class Thumb1InstrInfo : public ARMBaseInstrInfo {
|
||||||
Thumb1RegisterInfo RI;
|
ThumbRegisterInfo RI;
|
||||||
public:
|
public:
|
||||||
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
|
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
|
||||||
|
|
||||||
@ -36,7 +36,7 @@ public:
|
|||||||
/// such, whenever a client has an instance of instruction info, it should
|
/// such, whenever a client has an instance of instruction info, it should
|
||||||
/// always be able to get register info as well (through this method).
|
/// always be able to get register info as well (through this method).
|
||||||
///
|
///
|
||||||
const Thumb1RegisterInfo &getRegisterInfo() const override { return RI; }
|
const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
|
||||||
|
|
||||||
void copyPhysReg(MachineBasicBlock &MBB,
|
void copyPhysReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I, DebugLoc DL,
|
MachineBasicBlock::iterator I, DebugLoc DL,
|
||||||
|
@ -15,14 +15,14 @@
|
|||||||
#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
|
#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
|
||||||
|
|
||||||
#include "ARMBaseInstrInfo.h"
|
#include "ARMBaseInstrInfo.h"
|
||||||
#include "Thumb2RegisterInfo.h"
|
#include "ThumbRegisterInfo.h"
|
||||||
|
|
||||||
namespace llvm {
|
namespace llvm {
|
||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class ScheduleHazardRecognizer;
|
class ScheduleHazardRecognizer;
|
||||||
|
|
||||||
class Thumb2InstrInfo : public ARMBaseInstrInfo {
|
class Thumb2InstrInfo : public ARMBaseInstrInfo {
|
||||||
Thumb2RegisterInfo RI;
|
ThumbRegisterInfo RI;
|
||||||
public:
|
public:
|
||||||
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
|
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
|
||||||
|
|
||||||
@ -60,7 +60,7 @@ public:
|
|||||||
/// such, whenever a client has an instance of instruction info, it should
|
/// such, whenever a client has an instance of instruction info, it should
|
||||||
/// always be able to get register info as well (through this method).
|
/// always be able to get register info as well (through this method).
|
||||||
///
|
///
|
||||||
const Thumb2RegisterInfo &getRegisterInfo() const override { return RI; }
|
const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
|
||||||
|
|
||||||
private:
|
private:
|
||||||
void expandLoadStackGuard(MachineBasicBlock::iterator MI,
|
void expandLoadStackGuard(MachineBasicBlock::iterator MI,
|
||||||
|
@ -1,51 +0,0 @@
|
|||||||
//===-- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------------===//
|
|
||||||
//
|
|
||||||
// The LLVM Compiler Infrastructure
|
|
||||||
//
|
|
||||||
// This file is distributed under the University of Illinois Open Source
|
|
||||||
// License. See LICENSE.TXT for details.
|
|
||||||
//
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
//
|
|
||||||
// This file contains the Thumb-2 implementation of the TargetRegisterInfo
|
|
||||||
// class.
|
|
||||||
//
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
#include "Thumb2RegisterInfo.h"
|
|
||||||
#include "ARM.h"
|
|
||||||
#include "ARMSubtarget.h"
|
|
||||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
|
||||||
#include "llvm/CodeGen/MachineFunction.h"
|
|
||||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
||||||
#include "llvm/IR/Constants.h"
|
|
||||||
#include "llvm/IR/DerivedTypes.h"
|
|
||||||
#include "llvm/IR/Function.h"
|
|
||||||
#include "llvm/Target/TargetInstrInfo.h"
|
|
||||||
#include "llvm/Target/TargetMachine.h"
|
|
||||||
using namespace llvm;
|
|
||||||
|
|
||||||
Thumb2RegisterInfo::Thumb2RegisterInfo() : ARMBaseRegisterInfo() {}
|
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
||||||
/// specified immediate.
|
|
||||||
void
|
|
||||||
Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator &MBBI,
|
|
||||||
DebugLoc dl,
|
|
||||||
unsigned DestReg, unsigned SubIdx,
|
|
||||||
int Val,
|
|
||||||
ARMCC::CondCodes Pred, unsigned PredReg,
|
|
||||||
unsigned MIFlags) const {
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
|
||||||
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
|
||||||
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
|
||||||
const Constant *C = ConstantInt::get(
|
|
||||||
Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
|
|
||||||
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
|
||||||
|
|
||||||
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
|
||||||
.addReg(DestReg, getDefRegState(true), SubIdx)
|
|
||||||
.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
|
||||||
.setMIFlags(MIFlags);
|
|
||||||
}
|
|
@ -1,38 +0,0 @@
|
|||||||
//===- Thumb2RegisterInfo.h - Thumb-2 Register Information Impl -*- C++ -*-===//
|
|
||||||
//
|
|
||||||
// The LLVM Compiler Infrastructure
|
|
||||||
//
|
|
||||||
// This file is distributed under the University of Illinois Open Source
|
|
||||||
// License. See LICENSE.TXT for details.
|
|
||||||
//
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
//
|
|
||||||
// This file contains the Thumb-2 implementation of the TargetRegisterInfo
|
|
||||||
// class.
|
|
||||||
//
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
#ifndef LLVM_LIB_TARGET_ARM_THUMB2REGISTERINFO_H
|
|
||||||
#define LLVM_LIB_TARGET_ARM_THUMB2REGISTERINFO_H
|
|
||||||
|
|
||||||
#include "ARMBaseRegisterInfo.h"
|
|
||||||
|
|
||||||
namespace llvm {
|
|
||||||
|
|
||||||
class ARMSubtarget;
|
|
||||||
|
|
||||||
struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
|
|
||||||
public:
|
|
||||||
Thumb2RegisterInfo();
|
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
||||||
/// specified immediate.
|
|
||||||
void
|
|
||||||
emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
||||||
DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
|
||||||
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
|
||||||
unsigned MIFlags = MachineInstr::NoFlags) const override;
|
|
||||||
};
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
@ -1,4 +1,4 @@
|
|||||||
//===-- Thumb1RegisterInfo.cpp - Thumb-1 Register Information -------------===//
|
//===-- ThumbRegisterInfo.cpp - Thumb-1 Register Information -------------===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -12,7 +12,7 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#include "Thumb1RegisterInfo.h"
|
#include "ThumbRegisterInfo.h"
|
||||||
#include "ARMBaseInstrInfo.h"
|
#include "ARMBaseInstrInfo.h"
|
||||||
#include "ARMMachineFunctionInfo.h"
|
#include "ARMMachineFunctionInfo.h"
|
||||||
#include "ARMSubtarget.h"
|
#include "ARMSubtarget.h"
|
||||||
@ -38,32 +38,33 @@ extern cl::opt<bool> ReuseFrameIndexVals;
|
|||||||
|
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
Thumb1RegisterInfo::Thumb1RegisterInfo() : ARMBaseRegisterInfo() {}
|
ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}
|
||||||
|
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
||||||
const MachineFunction &MF) const {
|
const MachineFunction &MF) const {
|
||||||
|
if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
|
||||||
|
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
|
||||||
|
|
||||||
if (ARM::tGPRRegClass.hasSubClassEq(RC))
|
if (ARM::tGPRRegClass.hasSubClassEq(RC))
|
||||||
return &ARM::tGPRRegClass;
|
return &ARM::tGPRRegClass;
|
||||||
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
|
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
|
||||||
}
|
}
|
||||||
|
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
Thumb1RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
|
ThumbRegisterInfo::getPointerRegClass(const MachineFunction &MF,
|
||||||
const {
|
unsigned Kind) const {
|
||||||
|
if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only())
|
||||||
|
return ARMBaseRegisterInfo::getPointerRegClass(MF, Kind);
|
||||||
return &ARM::tGPRRegClass;
|
return &ARM::tGPRRegClass;
|
||||||
}
|
}
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
static void emitThumb1LoadConstPool(MachineBasicBlock &MBB,
|
||||||
/// specified immediate.
|
MachineBasicBlock::iterator &MBBI,
|
||||||
void Thumb1RegisterInfo::emitLoadConstPool(
|
DebugLoc dl, unsigned DestReg,
|
||||||
MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
|
unsigned SubIdx, int Val,
|
||||||
unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
||||||
unsigned PredReg, unsigned MIFlags) const {
|
unsigned MIFlags) {
|
||||||
assert((isARMLowRegister(DestReg) ||
|
|
||||||
isVirtualRegister(DestReg)) &&
|
|
||||||
"Thumb1 does not have ldr to high register");
|
|
||||||
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
MachineFunction &MF = *MBB.getParent();
|
||||||
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
||||||
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
||||||
@ -78,6 +79,42 @@ void Thumb1RegisterInfo::emitLoadConstPool(
|
|||||||
.setMIFlags(MIFlags);
|
.setMIFlags(MIFlags);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void emitThumb2LoadConstPool(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator &MBBI,
|
||||||
|
DebugLoc dl, unsigned DestReg,
|
||||||
|
unsigned SubIdx, int Val,
|
||||||
|
ARMCC::CondCodes Pred, unsigned PredReg,
|
||||||
|
unsigned MIFlags) {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
|
||||||
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
||||||
|
const Constant *C = ConstantInt::get(
|
||||||
|
Type::getInt32Ty(MBB.getParent()->getFunction()->getContext()), Val);
|
||||||
|
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
||||||
|
|
||||||
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
|
||||||
|
.addReg(DestReg, getDefRegState(true), SubIdx)
|
||||||
|
.addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
||||||
|
.setMIFlags(MIFlags);
|
||||||
|
}
|
||||||
|
|
||||||
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
|
/// specified immediate.
|
||||||
|
void ThumbRegisterInfo::emitLoadConstPool(
|
||||||
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl,
|
||||||
|
unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
|
||||||
|
unsigned PredReg, unsigned MIFlags) const {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
||||||
|
if (STI.isThumb1Only()) {
|
||||||
|
assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) &&
|
||||||
|
"Thumb1 does not have ldr to high register");
|
||||||
|
return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
|
||||||
|
PredReg, MIFlags);
|
||||||
|
}
|
||||||
|
return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
|
||||||
|
PredReg, MIFlags);
|
||||||
|
}
|
||||||
|
|
||||||
/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
|
/// emitThumbRegPlusImmInReg - Emits a series of instructions to materialize
|
||||||
/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
|
/// a destreg = basereg + immediate in Thumb code. Materialize the immediate
|
||||||
@ -312,12 +349,15 @@ static unsigned convertToNonSPOpcode(unsigned Opcode) {
|
|||||||
return Opcode;
|
return Opcode;
|
||||||
}
|
}
|
||||||
|
|
||||||
bool Thumb1RegisterInfo::
|
bool ThumbRegisterInfo::rewriteFrameIndex(MachineBasicBlock::iterator II,
|
||||||
rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
|
unsigned FrameRegIdx,
|
||||||
unsigned FrameReg, int &Offset,
|
unsigned FrameReg, int &Offset,
|
||||||
const ARMBaseInstrInfo &TII) const {
|
const ARMBaseInstrInfo &TII) const {
|
||||||
MachineInstr &MI = *II;
|
MachineInstr &MI = *II;
|
||||||
MachineBasicBlock &MBB = *MI.getParent();
|
MachineBasicBlock &MBB = *MI.getParent();
|
||||||
|
const MachineFunction &MF = *MBB.getParent();
|
||||||
|
assert(MF.getSubtarget<ARMSubtarget>().isThumb1Only() &&
|
||||||
|
"This isn't needed for thumb2!");
|
||||||
DebugLoc dl = MI.getDebugLoc();
|
DebugLoc dl = MI.getDebugLoc();
|
||||||
MachineInstrBuilder MIB(*MBB.getParent(), &MI);
|
MachineInstrBuilder MIB(*MBB.getParent(), &MI);
|
||||||
unsigned Opcode = MI.getOpcode();
|
unsigned Opcode = MI.getOpcode();
|
||||||
@ -381,10 +421,13 @@ rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
|
|||||||
return Offset == 0;
|
return Offset == 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
||||||
int64_t Offset) const {
|
int64_t Offset) const {
|
||||||
const MachineFunction &MF = *MI.getParent()->getParent();
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
||||||
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
||||||
|
if (!STI.isThumb1Only())
|
||||||
|
return ARMBaseRegisterInfo::resolveFrameIndex(MI, BaseReg, Offset);
|
||||||
|
|
||||||
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
|
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
|
||||||
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
||||||
unsigned i = 0;
|
unsigned i = 0;
|
||||||
@ -400,18 +443,20 @@ void Thumb1RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
|
|||||||
|
|
||||||
/// saveScavengerRegister - Spill the register so it can be used by the
|
/// saveScavengerRegister - Spill the register so it can be used by the
|
||||||
/// register scavenger. Return true.
|
/// register scavenger. Return true.
|
||||||
bool
|
bool ThumbRegisterInfo::saveScavengerRegister(
|
||||||
Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC,
|
||||||
MachineBasicBlock::iterator &UseMI,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
unsigned Reg) const {
|
unsigned Reg) const {
|
||||||
|
|
||||||
|
const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>();
|
||||||
|
if (!STI.isThumb1Only())
|
||||||
|
return ARMBaseRegisterInfo::saveScavengerRegister(MBB, I, UseMI, RC, Reg);
|
||||||
|
|
||||||
// Thumb1 can't use the emergency spill slot on the stack because
|
// Thumb1 can't use the emergency spill slot on the stack because
|
||||||
// ldr/str immediate offsets must be positive, and if we're referencing
|
// ldr/str immediate offsets must be positive, and if we're referencing
|
||||||
// off the frame pointer (if, for example, there are alloca() calls in
|
// off the frame pointer (if, for example, there are alloca() calls in
|
||||||
// the function, the offset will be negative. Use R12 instead since that's
|
// the function, the offset will be negative. Use R12 instead since that's
|
||||||
// a call clobbered register that we know won't be used in Thumb1 mode.
|
// a call clobbered register that we know won't be used in Thumb1 mode.
|
||||||
const ARMSubtarget &STI = MBB.getParent()->getSubtarget<ARMSubtarget>();
|
|
||||||
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
const TargetInstrInfo &TII = *STI.getInstrInfo();
|
||||||
DebugLoc DL;
|
DebugLoc DL;
|
||||||
AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
|
AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
|
||||||
@ -450,15 +495,18 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void ThumbRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||||
Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
||||||
int SPAdj, unsigned FIOperandNum,
|
int SPAdj, unsigned FIOperandNum,
|
||||||
RegScavenger *RS) const {
|
RegScavenger *RS) const {
|
||||||
unsigned VReg = 0;
|
|
||||||
MachineInstr &MI = *II;
|
MachineInstr &MI = *II;
|
||||||
MachineBasicBlock &MBB = *MI.getParent();
|
MachineBasicBlock &MBB = *MI.getParent();
|
||||||
MachineFunction &MF = *MBB.getParent();
|
MachineFunction &MF = *MBB.getParent();
|
||||||
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
|
||||||
|
if (!STI.isThumb1Only())
|
||||||
|
return ARMBaseRegisterInfo::eliminateFrameIndex(II, SPAdj, FIOperandNum,
|
||||||
|
RS);
|
||||||
|
|
||||||
|
unsigned VReg = 0;
|
||||||
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
|
const ARMBaseInstrInfo &TII = *STI.getInstrInfo();
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
DebugLoc dl = MI.getDebugLoc();
|
DebugLoc dl = MI.getDebugLoc();
|
@ -1,4 +1,4 @@
|
|||||||
//===- Thumb1RegisterInfo.h - Thumb-1 Register Information Impl -*- C++ -*-===//
|
//===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===//
|
||||||
//
|
//
|
||||||
// The LLVM Compiler Infrastructure
|
// The LLVM Compiler Infrastructure
|
||||||
//
|
//
|
||||||
@ -7,8 +7,9 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
//
|
//
|
||||||
// This file contains the Thumb-1 implementation of the TargetRegisterInfo
|
// This file contains the Thumb implementation of the TargetRegisterInfo
|
||||||
// class.
|
// class. With the exception of emitLoadConstPool Thumb2 tracks
|
||||||
|
// ARMBaseRegisterInfo, Thumb1 overloads the functions below.
|
||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
@ -22,9 +23,9 @@ namespace llvm {
|
|||||||
class ARMSubtarget;
|
class ARMSubtarget;
|
||||||
class ARMBaseInstrInfo;
|
class ARMBaseInstrInfo;
|
||||||
|
|
||||||
struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
|
||||||
public:
|
public:
|
||||||
Thumb1RegisterInfo();
|
ThumbRegisterInfo();
|
||||||
|
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
getLargestLegalSuperClass(const TargetRegisterClass *RC,
|
Loading…
Reference in New Issue
Block a user