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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Make generation of stack-slot loads and copies less ugly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12742 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -40,26 +40,23 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
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int SparcV8RegisterInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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assert (RC == SparcV8::IntRegsRegisterClass
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&& "Can only load 32-bit registers from stack slots");
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MachineInstr *I =
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BuildMI (V8::LDmr, 2).addReg (DestReg).addFrameIndex (FrameIdx).addSImm (0);
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MBB.insert(MBBI, I);
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BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
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return 1;
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}
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int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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assert (RC == SparcV8::IntRegsRegisterClass
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&& "Can only copy 32-bit registers");
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MBB.insert (MBBI,
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BuildMI (V8::ORrr, 3, DestReg).addReg (V8::G0).addReg (SrcReg));
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BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
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return -1;
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}
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@ -40,26 +40,23 @@ int SparcV8RegisterInfo::storeRegToStackSlot(
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int SparcV8RegisterInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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assert (RC == SparcV8::IntRegsRegisterClass
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&& "Can only load 32-bit registers from stack slots");
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MachineInstr *I =
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BuildMI (V8::LDmr, 2).addReg (DestReg).addFrameIndex (FrameIdx).addSImm (0);
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MBB.insert(MBBI, I);
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BuildMI (MBB, I, V8::LDmr, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
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return 1;
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}
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int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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assert (RC == SparcV8::IntRegsRegisterClass
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&& "Can only copy 32-bit registers");
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MBB.insert (MBBI,
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BuildMI (V8::ORrr, 3, DestReg).addReg (V8::G0).addReg (SrcReg));
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BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
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return -1;
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}
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