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AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin form
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196914 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
9f84f21a4c
commit
89458ced87
@ -3047,30 +3047,15 @@ let TargetPrefix = "x86" in {
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// AVX-512 conflict detection
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let TargetPrefix = "x86" in {
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def int_x86_avx512_conflict_d_512 : GCCBuiltin<"__builtin_ia32_conflictd512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty],
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[]>;
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def int_x86_avx512_conflict_d_mask_512 :
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GCCBuiltin<"__builtin_ia32_mask_conflictd512">,
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def int_x86_avx512_mask_conflict_d_512 :
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GCCBuiltin<"__builtin_ia32_vpconflictsi_512_mask">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
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llvm_v16i1_ty, llvm_v16i32_ty],
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llvm_v16i32_ty, llvm_i16_ty],
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[]>;
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def int_x86_avx512_conflict_d_maskz_512:
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GCCBuiltin<"__builtin_ia32_maskz_conflictd512">,
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Intrinsic<[llvm_v16i32_ty], [llvm_v16i1_ty, llvm_v16i32_ty],
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[]>;
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def int_x86_avx512_conflict_q_512 : GCCBuiltin<"__builtin_ia32_conflictq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty],
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[]>;
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def int_x86_avx512_conflict_q_mask_512 :
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GCCBuiltin<"__builtin_ia32_mask_conflictq512">,
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def int_x86_avx512_mask_conflict_q_512 :
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GCCBuiltin<"__builtin_ia32_vpconflictdi_512_mask">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
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llvm_v8i1_ty, llvm_v8i64_ty],
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[]>;
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def int_x86_avx512_conflict_q_maskz_512:
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GCCBuiltin<"__builtin_ia32_maskz_conflictq512">,
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Intrinsic<[llvm_v8i64_ty], [llvm_v8i1_ty, llvm_v8i64_ty],
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llvm_v8i64_ty, llvm_i8_ty],
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[]>;
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}
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@ -3459,18 +3459,17 @@ defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
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EVEX_CD8<64, CD8VF>;
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multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
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RegisterClass RC, RegisterClass KRC, PatFrag memop_frag,
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X86MemOperand x86memop, PatFrag scalar_mfrag,
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X86MemOperand x86scalar_mop, string BrdcstStr,
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Intrinsic Int, Intrinsic maskInt, Intrinsic maskzInt> {
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RegisterClass RC, RegisterClass KRC,
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X86MemOperand x86memop,
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X86MemOperand x86scalar_mop, string BrdcstStr> {
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def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} |${dst}, $src}"),
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[(set RC:$dst, (Int RC:$src))]>, EVEX;
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[]>, EVEX;
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def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst}|${dst}, $src}"),
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[(set RC:$dst, (Int (memop_frag addr:$src)))]>, EVEX;
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[]>, EVEX;
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def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86scalar_mop:$src),
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!strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
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@ -3480,13 +3479,12 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
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(ins KRC:$mask, RC:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[(set RC:$dst, (maskzInt KRC:$mask, RC:$src))]>, EVEX, EVEX_KZ;
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[]>, EVEX, EVEX_KZ;
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def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, x86memop:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[(set RC:$dst, (maskzInt KRC:$mask, (memop_frag addr:$src)))]>,
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EVEX, EVEX_KZ;
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[]>, EVEX, EVEX_KZ;
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def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, x86scalar_mop:$src),
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!strconcat(OpcodeStr, "\t{${src}", BrdcstStr,
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@ -3499,12 +3497,12 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
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(ins RC:$src1, KRC:$mask, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
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[(set RC:$dst, (maskInt RC:$src1, KRC:$mask, RC:$src2))]>, EVEX, EVEX_K;
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[]>, EVEX, EVEX_K;
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def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, x86memop:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
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[(set RC:$dst, (maskInt RC:$src1, KRC:$mask, (memop_frag addr:$src2)))]>, EVEX, EVEX_K;
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[]>, EVEX, EVEX_K;
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def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
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!strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
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@ -3515,16 +3513,22 @@ multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
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let Predicates = [HasCDI] in {
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defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
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memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
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int_x86_avx512_conflict_d_512,
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int_x86_avx512_conflict_d_mask_512,
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int_x86_avx512_conflict_d_maskz_512>,
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i512mem, i32mem, "{1to16}">,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
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memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
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int_x86_avx512_conflict_q_512,
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int_x86_avx512_conflict_q_mask_512,
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int_x86_avx512_conflict_q_maskz_512>,
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i512mem, i64mem, "{1to8}">,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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}
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def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
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GR16:$mask),
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(VPCONFLICTDrrk VR512:$src1,
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(v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
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def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
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GR8:$mask),
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(VPCONFLICTQrrk VR512:$src1,
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(v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
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@ -3029,6 +3029,22 @@ unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
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(X86::VK8RegClass.contains(SrcReg) ||
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X86::VK16RegClass.contains(SrcReg)))
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return X86::KMOVWkk;
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if ((X86::VK8RegClass.contains(DestReg) ||
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X86::VK16RegClass.contains(DestReg)) &&
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(X86::GR32RegClass.contains(SrcReg) ||
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X86::GR16RegClass.contains(SrcReg) ||
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X86::GR8RegClass.contains(SrcReg))) {
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SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
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return X86::KMOVWkr;
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}
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if ((X86::GR32RegClass.contains(DestReg) ||
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X86::GR16RegClass.contains(DestReg) ||
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X86::GR8RegClass.contains(DestReg)) &&
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(X86::VK8RegClass.contains(SrcReg) ||
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X86::VK16RegClass.contains(SrcReg))) {
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DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
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return X86::KMOVWrk;
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}
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return 0;
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}
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@ -319,27 +319,37 @@ define <8 x i64> @test_x86_pmins_q(<8 x i64> %a0, <8 x i64> %a1) {
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declare <8 x i64> @llvm.x86.avx512.pmins.q(<8 x i64>, <8 x i64>) nounwind readonly
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define <16 x i32> @test_conflict_d(<16 x i32> %a) {
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; CHECK: movw $-1, %ax
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; CHECK: vpxor
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; CHECK: vpconflictd
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%res = call <16 x i32> @llvm.x86.avx512.conflict.d.512(<16 x i32> %a)
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%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 -1)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.conflict.d.512(<16 x i32>) nounwind readonly
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define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
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; CHECK: vpconflictd %zmm0, %zmm0 {%k1} {z}
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%vmask = bitcast i16 %mask to <16 x i1>
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%res = call <16 x i32> @llvm.x86.avx512.conflict.d.maskz.512(<16 x i1> %vmask, <16 x i32> %a)
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ret <16 x i32> %res
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}
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declare <16 x i32> @llvm.x86.avx512.conflict.d.maskz.512(<16 x i1>,<16 x i32>) nounwind readonly
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declare <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly
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define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
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; CHECK: vpconflictq {{.*}} {%k1}
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%vmask = bitcast i8 %mask to <8 x i1>
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%res = call <8 x i64> @llvm.x86.avx512.conflict.q.mask.512(<8 x i64> %b, <8 x i1> %vmask, <8 x i64> %a)
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define <8 x i64> @test_conflict_q(<8 x i64> %a) {
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; CHECK: movb $-1, %al
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; CHECK: vpxor
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; CHECK: vpconflictq
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%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> zeroinitializer, i8 -1)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readonly
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define <16 x i32> @test_maskz_conflict_d(<16 x i32> %a, i16 %mask) {
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; CHECK: vpconflictd
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%res = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a, <16 x i32> zeroinitializer, i16 %mask)
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ret <16 x i32> %res
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}
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define <8 x i64> @test_mask_conflict_q(<8 x i64> %a, <8 x i64> %b, i8 %mask) {
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; CHECK: vpconflictq
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%res = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a, <8 x i64> %b, i8 %mask)
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ret <8 x i64> %res
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}
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declare <8 x i64> @llvm.x86.avx512.conflict.q.mask.512(<8 x i64>, <8 x i1>,<8 x i64>) nounwind readonly
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define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x float> %a2) {
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; CHECK: vblendmps
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@ -347,6 +357,7 @@ define <16 x float> @test_x86_mask_blend_ps_512(i16 %a0, <16 x float> %a1, <16 x
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%res = call <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x i1> %m0, <16 x float> %a1, <16 x float> %a2) ; <<16 x float>> [#uses=1]
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ret <16 x float> %res
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}
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declare <16 x float> @llvm.x86.avx512.mask.blend.ps.512(<16 x i1> %a0, <16 x float> %a1, <16 x float> %a2) nounwind readonly
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define <8 x double> @test_x86_mask_blend_pd_512(i8 %a0, <8 x double> %a1, <8 x double> %a2) {
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