From 894fa802f5052873d9788f68a09fdbdfa79d5072 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 31 Mar 2014 18:21:13 +0000 Subject: [PATCH] R600: Add target nodes for BFM and BFI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205235 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/AMDGPUISelLowering.cpp | 2 ++ lib/Target/R600/AMDGPUISelLowering.h | 2 ++ lib/Target/R600/AMDGPUInstrInfo.td | 2 ++ lib/Target/R600/EvergreenInstructions.td | 5 ++++- lib/Target/R600/SIInstructions.td | 6 ++++-- 5 files changed, 14 insertions(+), 3 deletions(-) diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index 797063d0e10..2fbf6257241 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -1176,6 +1176,8 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(UMIN) NODE_NAME_CASE(BFE_U32) NODE_NAME_CASE(BFE_I32) + NODE_NAME_CASE(BFI) + NODE_NAME_CASE(BFM) NODE_NAME_CASE(URECIP) NODE_NAME_CASE(DOT4) NODE_NAME_CASE(EXPORT) diff --git a/lib/Target/R600/AMDGPUISelLowering.h b/lib/Target/R600/AMDGPUISelLowering.h index 48298f20979..a01961601de 100644 --- a/lib/Target/R600/AMDGPUISelLowering.h +++ b/lib/Target/R600/AMDGPUISelLowering.h @@ -186,6 +186,8 @@ enum { DOT4, BFE_U32, // Extract range of bits with zero extension to 32-bits. BFE_I32, // Extract range of bits with sign extension to 32-bits. + BFI, // (src0 & src1) | (~src0 & src2) + BFM, // Insert a range of bits into a 32-bit word. TEXTURE_FETCH, EXPORT, CONST_ADDRESS, diff --git a/lib/Target/R600/AMDGPUInstrInfo.td b/lib/Target/R600/AMDGPUInstrInfo.td index 2138bd23a36..69d80592cf8 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.td +++ b/lib/Target/R600/AMDGPUInstrInfo.td @@ -89,4 +89,6 @@ def AMDGPUround : SDNode<"ISD::FROUND", def AMDGPUbfe_u32 : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>; def AMDGPUbfe_i32 : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>; +def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>; +def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>; diff --git a/lib/Target/R600/EvergreenInstructions.td b/lib/Target/R600/EvergreenInstructions.td index 384b98eebe8..93151b4b51e 100644 --- a/lib/Target/R600/EvergreenInstructions.td +++ b/lib/Target/R600/EvergreenInstructions.td @@ -281,8 +281,11 @@ def BFE_INT_eg : R600_3OP <0x4, "BFE_INT", // XXX: This pattern is broken, disabling for now. See comment in // AMDGPUInstructions.td for more info. // def : BFEPattern ; +def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", + [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], + VecALU +>; -def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", [], VecALU>; defm : BFIPatterns ; def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 55d31eaa5bf..1a1676f8f56 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -989,7 +989,8 @@ defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>; } // End isCommutable = 1 -defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; +defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", + [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; @@ -1064,7 +1065,8 @@ def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))]>; } -def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; +def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", + [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))]>; defm : BFIPatterns ; def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))]