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Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value

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must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-05-31 03:33:27 +00:00
parent 4e694c96f1
commit 895c1e2dee
7 changed files with 32 additions and 8 deletions
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2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -232,6 +232,8 @@ namespace {
unsigned Op) const { return 0; }
unsigned getMsbOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
unsigned getSsatBitPosValue(const MachineInstr &MI,
unsigned Op) const { return 0; }
uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
const {return 0; }
uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)

10
lib/Target/ARM/ARMInstrInfo.td
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@ -475,6 +475,12 @@ def width_imm : Operand<i32>, ImmLeaf<i32, [{
let EncoderMethod = "getMsbOpValue";
}
def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
return Imm > 0 && Imm <= 32;
}]> {
let EncoderMethod = "getSsatBitPosValue";
}
// Define ARM specific addressing modes.
def MemMode2AsmOperand : AsmOperandClass {
@ -2455,7 +2461,7 @@ def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
// Signed/Unsigned saturate -- for disassembly only
def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;
@ -2471,7 +2477,7 @@ def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
let Inst{3-0} = Rn;
}
def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
[/* For disassembly only; pattern left blank */]> {
bits<4> Rd;

12
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1973,9 +1973,9 @@ class T2SatI<dag oops, dag iops, InstrItinClass itin,
}
def t2SSAT: T2SatI<
(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
[/* For disassembly only; pattern left blank */]> {
(outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn, shift_imm:$sh),
NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{25-22} = 0b1100;
let Inst{20} = 0;
@ -1983,9 +1983,9 @@ def t2SSAT: T2SatI<
}
def t2SSAT16: T2SatI<
(outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary,
"ssat16", "\t$Rd, $sat_imm, $Rn",
[/* For disassembly only; pattern left blank */]> {
(outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
"ssat16", "\t$Rd, $sat_imm, $Rn",
[/* For disassembly only; pattern left blank */]> {
let Inst{31-27} = 0b11110;
let Inst{25-22} = 0b1100;
let Inst{20} = 0;

10
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -269,6 +269,9 @@ public:
unsigned getMsbOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getSsatBitPosValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const;
unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
@ -1123,6 +1126,13 @@ getMsbOpValue(const MCInst &MI, unsigned Op,
return msb;
}
unsigned ARMMCCodeEmitter::
getSsatBitPosValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {
// For ssat instructions, the bit position should be encoded decremented by 1
return MI.getOperand(Op).getImm()-1;
}
unsigned ARMMCCodeEmitter::
getRegisterListOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl<MCFixup> &Fixups) const {

3
test/MC/ARM/arm_instructions.s
View File

@ -312,3 +312,6 @@
@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1]
ldrexd r0, r1, [r0]
@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
ssat16 r0, #7, r0

2
test/MC/ARM/thumb2.s
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@ -300,3 +300,5 @@
ldrex r0, [r0]
@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0xd0,0xe8,0x7f,0x01]
ldrexd r0, r1, [r0]
@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x20,0xf3,0x06,0x00]
ssat16 r0, #7, r0

1
utils/TableGen/EDEmitter.cpp
View File

@ -596,6 +596,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("t_adrlabel");
IMM("t2adrlabel");
IMM("shift_imm");
IMM("ssat_imm");
IMM("neon_vcvt_imm32");
IMM("shr_imm8");
IMM("shr_imm16");