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Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,
instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170538 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -593,7 +593,7 @@ namespace {
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/// getRegisterType member function, however when with physical registers
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/// it is necessary to have a separate record of the types.
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///
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SmallVector<EVT, 4> RegVTs;
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SmallVector<MVT, 4> RegVTs;
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/// Regs - This list holds the registers assigned to the values.
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/// Each legal or promoted value requires one register, and each
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@ -604,7 +604,7 @@ namespace {
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RegsForValue() {}
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RegsForValue(const SmallVector<unsigned, 4> ®s,
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EVT regvt, EVT valuevt)
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MVT regvt, EVT valuevt)
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: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
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RegsForValue(LLVMContext &Context, const TargetLowering &tli,
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@ -625,7 +625,7 @@ namespace {
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/// areValueTypesLegal - Return true if types of all the values are legal.
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bool areValueTypesLegal(const TargetLowering &TLI) {
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for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT RegisterVT = RegVTs[Value];
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MVT RegisterVT = RegVTs[Value];
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if (!TLI.isTypeLegal(RegisterVT))
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return false;
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}
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@ -687,7 +687,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
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// Copy the legal parts from the registers.
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EVT ValueVT = ValueVTs[Value];
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unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
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EVT RegisterVT = RegVTs[Value];
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MVT RegisterVT = RegVTs[Value];
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Parts.resize(NumRegs);
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for (unsigned i = 0; i != NumRegs; ++i) {
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@ -772,7 +772,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
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for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
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EVT ValueVT = ValueVTs[Value];
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unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
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EVT RegisterVT = RegVTs[Value];
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MVT RegisterVT = RegVTs[Value];
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ISD::NodeType ExtendKind =
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TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
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@ -840,7 +840,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
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for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
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unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
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EVT RegisterVT = RegVTs[Value];
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MVT RegisterVT = RegVTs[Value];
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for (unsigned i = 0; i != NumRegs; ++i) {
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assert(Reg < Regs.size() && "Mismatch in # registers expected");
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Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
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@ -1765,7 +1765,7 @@ void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
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}
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B.RegVT = VT.getSimpleVT();
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B.Reg = FuncInfo.CreateReg(B.RegVT.getSimpleVT());
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B.Reg = FuncInfo.CreateReg(B.RegVT);
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SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
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B.Reg, Sub);
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@ -1799,7 +1799,7 @@ void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
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unsigned Reg,
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BitTestCase &B,
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MachineBasicBlock *SwitchBB) {
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EVT VT = BB.RegVT;
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MVT VT = BB.RegVT;
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SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
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Reg, VT);
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SDValue Cmp;
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@ -5748,7 +5748,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
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// Try to convert to the first EVT that the reg class contains. If the
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// types are identical size, use a bitcast to convert (e.g. two differing
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// vector types).
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EVT RegVT = *PhysReg.second->vt_begin();
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MVT RegVT = *PhysReg.second->vt_begin();
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if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
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OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
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RegVT, OpInfo.CallOperand);
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@ -5758,8 +5758,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
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// bitcast to the corresponding integer type. This turns an f64 value
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// into i64, which can be passed with two i32 values on a 32-bit
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// machine.
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RegVT = EVT::getIntegerVT(Context,
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OpInfo.ConstraintVT.getSizeInBits());
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RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
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OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
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RegVT, OpInfo.CallOperand);
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OpInfo.ConstraintVT = RegVT;
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@ -5769,7 +5768,7 @@ static void GetRegistersForValue(SelectionDAG &DAG,
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NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
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}
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EVT RegVT;
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MVT RegVT;
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EVT ValueVT = OpInfo.ConstraintVT;
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// If this is a constraint for a specific physical register, like {r17},
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@ -262,7 +262,7 @@ private:
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struct BitTestBlock {
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BitTestBlock(APInt F, APInt R, const Value* SV,
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unsigned Rg, EVT RgVT, bool E,
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unsigned Rg, MVT RgVT, bool E,
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
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@ -271,7 +271,7 @@ private:
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APInt Range;
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const Value *SValue;
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unsigned Reg;
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EVT RegVT;
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MVT RegVT;
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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